View HT56RB688_4395217.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces HT56RB688 revision: 1.00 date: december 2, 2011
table of contents technical document ...........................................................................7 features ...............................................................................................7 general description ............................................................................8 block diagram .....................................................................................8 pin assignment ...................................................................................9 pin description ..................................................................................10 absolute maximum ratings .............................................................12 d.c. characteristics ..........................................................................13 a.c. characteristics ..........................................................................16 a/d converter characteristics .........................................................18 power-on reset characteristics ......................................................18 dc/dc converter and ldo electrical characteristics ...................19 system architecture .........................................................................21 clocking and pipelining....................................................................21 program counter ..................................................................................................22 stack ....................................................................................................................23 arithmetic and logic unit alu ...........................................................................23 program memory...............................................................................24 structure ...............................................................................................................24 special vectors .....................................................................................................24 look-up table .......................................................................................................26 table program example .....................................................................................26 data memory......................................................................................27 structure ...............................................................................................................28 general purpose data memory ............................................................................28 special purpose data memory .............................................................................28 display memory ....................................................................................................28 special function registers ..............................................................30 indirect addressing registers iar0, iar1 ..........................................................30 memory pointers mp0, mp1 ..............................................................................30 bank pointer bp ................................................................................................31 accumulator acc ..............................................................................................31 rev. 1.00 2 december 2, 2011 contents
program counter low register pcl..................................................................31 look-up table registers tblp, tbhp, tblh .....................................................32 status register status ...................................................................................32 interrupt control registers ....................................................................................33 timer/event counter registers .............................................................................33 input/output ports and control registers .............................................................33 pulse width modulator registers ..........................................................................33 a/d converter registers adrl, adrh, adcr, acsr ......................................33 serial interface module registers .........................................................................34 port a wake-up register pawu ........................................................................34 pull-high registers papu, pbpu, pcpu, pdpu, pepu, pfpu .......................34 clock control register clkmod .......................................................................34 lcd/led registers lcdctrl, ledctrl, lcdio ...........................................34 miscellaneous register misc0, misc1 .............................................................34 input/output ports.............................................................................34 pull-high resistors ................................................................................................35 port a wake-up ....................................................................................................35 port a open drain function ..................................................................................36 i/o port control registers .....................................................................................36 pin-shared functions ............................................................................................37 i/o pin structures .................................................................................................37 programming considerations ...............................................................................39 lcd and led driver ..........................................................................39 display memory ....................................................................................................40 lcd/led registers ..............................................................................................41 lcd reset function .............................................................................................41 clock source ........................................................................................................42 lcd driver output ................................................................................................42 led driver output ................................................................................................43 lcd voltage source and biasing ..........................................................................44 programming considerations ...............................................................................46 timer/event counters .......................................................................50 configuring the timer/event counter input clock source .....................................51 timer registers tmr0, tmr1l/tmr1h, tmr2, tmr3 .....................................51 timer control registers tmr0c, tmr1c, tmr2c, tmr3c .............................52 configuring the timer mode .................................................................................53 configuring the event counter mode ....................................................................54 configuring the pulse width measurement mode .................................................54 programmable frequency divider pfd .............................................................55 prescaler ..............................................................................................................56 i/o interfacing .......................................................................................................56 timer/event counter pins internal filter ...............................................................56 contents rev. 1.00 3 december 2, 2011
programming considerations ...............................................................................57 timer program example .......................................................................................58 pulse width modulator .....................................................................59 pwm overview ....................................................................................................59 8+4 pwm mode modulation .................................................................................60 pwm output control ............................................................................................60 pwm register pairs pwmnh/pwmnl (n=0~3) .................................................61 pwm programming example ...............................................................................61 analog to digital converter..............................................................62 a/d overview .......................................................................................................62 a/d converter data registers adrl, adrh .....................................................62 a/d converter control registers adcr, adpcr, acsr ..................................63 a/d input pins ......................................................................................................65 initialising the a/d converter ................................................................................65 programming considerations ...............................................................................67 a/d programming example ..................................................................................67 a/d transfer function ...........................................................................................69 serial interface function sim ........................................................70 spi interface .........................................................................................................70 spi registers .......................................................................................................75 spi control register simnctl2 ........................................................................78 spi communication ..............................................................................................79 i 2 c interface .........................................................................................................79 i 2 c address register simnar ...........................................................................81 i 2 c bus communication ........................................................................................82 peripheral clock output ...................................................................86 peripheral clock operation ...................................................................................86 buzzer.................................................................................................87 pa0/pa1 pin function control ..............................................................................87 interrupts............................................................................................89 interrupt registers ................................................................................................90 interrupt operation ...............................................................................................93 interrupt priority .....................................................................................................93 external interrupt ..................................................................................................94 external peripheral interrupt .................................................................................95 timer/event counter interrupt ..............................................................................95 a/d interrupt .........................................................................................................96 smart card interrupt .............................................................................................96 smart card insertion/removal interrupt ...............................................................96 sim (spi/i 2 c interface) interrupts .........................................................................96 multi-function interrupt ..........................................................................................97 rev. 1.00 4 december 2, 2011 contents
real time clock interrupt .....................................................................................97 time base interrupt ..............................................................................................98 programming considerations ...............................................................................99 reset and initialisation ...................................................................100 reset functions .................................................................................................100 reset initial conditions .......................................................................................102 oscillator..........................................................................................106 system clock configurations ..............................................................................106 external crystal/ ceramic oscillator hxt .......................................................106 external rc oscillator erc .............................................................................107 internal rc oscillator hirc .............................................................................107 internal 32khz rc oscillator lirc ...................................................................107 external 32.768khz oscillator lxt ..................................................................108 lxt oscillator low power function ....................................................................109 external oscillator ec......................................................................................109 system operating modes ...............................................................109 clock sources ....................................................................................................109 operating modes ................................................................................................112 power down mode and wake-up ...................................................113 power down mode .............................................................................................113 entering the power down mode .........................................................................113 standby current considerations .........................................................................113 wake-up .............................................................................................................113 low voltage detector lvd ...........................................................114 lvd operation ....................................................................................................114 watchdog timer...............................................................................115 watchdog timer operation .................................................................................115 clearing the watchdog timer ..............................................................................116 usb interface ...................................................................................117 usb operation ...................................................................................................117 usb status and control registers ......................................................................117 usb register summary ......................................................................................118 usb interface suspend mode and wake-up ......................................................126 usb interrupt structure .....................................................................................127 digital to analog converter dac ................................................128 operation ...........................................................................................................128 dc/dc converter and ldo .............................................................129 dc2dc register .................................................................................................129 contents rev. 1.00 5 december 2, 2011
smart card interface .......................................................................130 interface pins .....................................................................................................130 card detection ...................................................................................................130 internal time counter etu, gtc, wtc ...........................................................131 elementary time unit etu ..............................................................................131 guard time counter gtc................................................................................132 waiting time counter wtc ............................................................................132 uart interface ...................................................................................................133 power control .....................................................................................................134 smart card interrupt structure ............................................................................135 programming considerations .............................................................................136 smart card interface status and control registers ............................................136 configuration options ....................................................................145 application circuits ........................................................................147 instruction set .................................................................................148 introduction .........................................................................................................148 instruction timing ...............................................................................................148 moving and transferring data ............................................................................148 arithmetic operations .........................................................................................148 logical and rotate operations ...........................................................................148 branches and control transfer ...........................................................................149 bit operations .....................................................................................................149 table read operations .......................................................................................149 other operations ................................................................................................149 instruction set summary ....................................................................................150 instruction definition ......................................................................152 package information .......................................................................162 144-pin lqfp (20mm 20mm) outline dimensions .............................................162 rev. 1.00 6 december 2, 2011 contents
technical document application note ha0075e mcu reset and oscillator circuits application note features operating voltage: f sys =32.768khz: 2.2v~5.5v f sys =4mhz: 2.2v~5.5v f sys =12mhz: 3.0v~5.5v f sys =20mhz: 4.5v~5.5v operating current: f sys =1mhz at 3v, 170 a, typ. otp program memory: 48k 16 ram data memory: 3840 8 12 levels subroutine nesting up to 48 bidirectional i/o lines tinypower technology for low power operation three pin-shared external interrupts lines three 8-bit programmable timer/event counters with overflow interrupt and 7-stage prescaler one 16-bit programmable timer/event counters with overflow interrupt external crystal (hxt), rc (erc) and 32.768khz (lxt) crystal oscillators internal high speed rc oscillator - hirc fully integrated rc 32khz oscillator - lirc externally supplied system clock option - ec watchdog timer function pfd/buzzer for audio frequency generation dual serial interface modules (sim): spi and i 2 c lcd and led driver function: 80 16 or 88 8 4 operating modes: normal, slow, idle and sleep 8-channel 12-bit resolution a/d converter 4-channel 12-bit pwm outputs 12-bit d/a converter with 8-level volume control usb interface fully compliant with usb 1.1 full-speed specification support 6 endpoints including endpoint 0 support interrupt, control and bulk transfer 160 bytes total fifo size - 8, 8, 8, 64, 8 and 64 bytes for endpoint0~endpoint 5 respectively smartcard interface compatible with and certifiable to the iso 7816-3 standards dc/dc converter and ldo function low voltage reset function: 2.1v, 3.15v, 4.2v low voltage detect function: 2.2v, 3.3v, 4.4v bit manipulation instruction table read instructions 63 powerful instructions up to 0.2 s instruction cycle with 20mhz system clock at v dd =5v all instructions executed in one or two machine cycles power down and wake-up functions to reduce power consumption package type: 144-pin lqfp HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 7 december 2, 2011
general description the tinypower tm a/d type 8-bit high performance risc architecture microcontroller with lcd/led driver is specifically designed for applications that interface directly to analog signals and which require an lcd or led interface. the device includes analog features such as an integrated multi-channel analog to digital converter, 12-bit digital to analog converter, lcd/led driver, dc/dc converter and ldo. with their fully integrated spi and i 2 c functions, designers are provided with a means of easy communication with external peripheral hardware. the benefits of integrated analog features such as a/d, lcd, etc., and pwm functions, in addition to low power consumption, high performance, i/o flexibility and low-cost, provides the device with the versatility for a wide range of products in the home appliance and industrial application areas. some of these products could include electronic metering, environmental monitoring, handheld instruments, electronically controlled tools, motor driving in addition to many others. the device contains a usb full-speed interface to allow data communication with an external usb host controller. it is particularly suitable for applications which require data communication between pcs and peripheral usb hardware. this device also includes a smartcard interface, which is compatible with and certified to iso 7816 standards, to provide communication with various types of smart card. the unique holtek tinypower technology also offers the advantages of extremely low current consumption characteristics, an extremely important consideration in the present trend for low power battery powered applications. the usual holtek mcu features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc., combine to ensure user applications require a minimum of external components. block diagram rev. 1.00 8 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces

! " # $ % &
$ & ' ( ) ! " * + , - . / 0 1

& ' / 2 % 3 4 % 3 4 ' ' & $ ( ' & ' ( % '
5 ' % ! ' & % ! ' '
(
pin assignment HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 9 december 2, 2011

6 6 6 6 $ 7 & + & $ 6 7 $ 8 & * & * & $ 6 8 $ . & 9 & $ 6 . $ - & : & $ 6 - & 4 ! 5 $ 4 ' ' 4 ' ' 4 $ 4 * & 7 + & * : & + 9 & : ' ! 7 % ; ' 4 4 4 ! % 5 4 % ' 9 : + * 7 8 . - ! < : . ! < : - ! < : ! < : = ! < + 9 ! < + : ! < + + ! < + * ! < + 7 ! < + 8 ! < + . ! < + - ! < + ! < + = ! < * 9 ! < * : ! < * + ! < * * ! < * 7 ! < * 8 ! < * . ! < * - ! < * ! < * = ! < 7 9 ! < 7 : ! < 7 + ! < 7 * ! < 7 7 ! < 7 8 ! < 7 . ! < 7 - ! < 7 ! < 7 = ! < 8 9 ! < 8 : ! < : 8 ! < : 7 ! < : * ! < : + ! < : : ! < : 9 ! < = ! < ! < - ! < . ! < 8 ! < 7 ! < * ! < + ! < : ! < 9 - & ! . & > + & 6 8 & : & % ; 7 & 9 & 9 2 9 & ; 9 & % 9 2 : & & % 9 2 + & ' 9 2 * & 4 ' ' 2 7 & ' : 2 8 & ' : & ' $ : 2 . & ; : & % : 2 - & : ' ' 4 * * $ 9 & 2 ? & 6 9 & $ 6 9 $ : & 2 ? & 6 : & $ 6 : $ + & $ ' & $ 6 + $ * & 5 ' & $ 6 * 6 ! < 8 + ! < 8 * ! < 8 7 ! < 8 8 ! < 8 . ! < 8 - ! < 8 . ! < 8 = ! < . 9 ! < . : ! < . + ! < . * ! < . 7 ! < . 8 ! < . . ! < . - ! < . ! < . = ! < - 9 ! < - : ! < - + ! < - * ! < - 7 < ! - 8 ! < - . ! < - - ! < - ! < - = : 8 : 7 : * : + : : : 9 = 6 : 9 = : : 7 7 * . : 9 - * * - - +
pin description the following table depicts the pins common to all devices. pin name i/o configuration option description input/output pa0/bz/int0/an0 pa1/bz /int1/an1 pa2/aud/an2 pa3/pfd/an3 pa4/tmr2/an4 pa5/tmr3/pwm3/an5 pa6/tmr0/an6 pa7/tmr1/an7/vref i/o bz/bz pfd bidirectional 8-bit input/output port. each individual bit on this port can be configured as a wake-up input by the pawu register control bit. software instructions determine if the pin is a cmos output or schmitt trigger input. a pull-high resistor can be connected to each pin determined by the papu register. port a is pin-shared with the a/d input pins. the a/d inputs are selected via software instructions. once a port a line is selected as an a/d input, the i/o function and pull-high resistor are disabled automatically. the bz/int0, bz /int1, pfd, tmr2, tmr3/pwm3, tmr0 and tmr1 are pin-shared with pa0, pa1, pa3 and pa4~pa7 respectively. aud is the audio output pin from the d/a converter and pin-shared with pa2. when the d/a-converter is enabled, the pa2 i/o function will be disabled automatically, including any pull-high resistors. if the d/a converter output, aud, and the a/d converter input, an2, are both enabled, then the d/a converter output will be connected to the an2 input channel allowing the d/a output to be measured by the a/d converter. vref is the adc reference voltage input pin. the vrefs bit in the acsr register is used to select either vref or avdd as the adc reference voltage. pb0/sck0/scl0 pb1/sdi0/sda0 pb2/sdo0 pb3/vddio * pb4/sdo1 pb5/sdi1/sda1 pb6/sck1/scl1 pb7/scs1 i/o vddio sim0 sim1 bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a pull-high resistor can be connected to each pin by the pbpu register. sdo1, sdi1/sda1, sck1/scl1 and scs1 are the the sim1 interface pins, pin-shared with pb4~pb7 respectively and enabled by a configuration option, as well as the sim0 interface pins. when the configuration option enables the sim function, the i/o function will be disabled. the vddio pin is an alternate power input pin for certain interface functions, for example the 3.3v mxic serial flash memory. it is pin-shared with pb3. a configuration option is used to determine if pb3 is selected to be an i/o pin or the alternate power pin vddio. when pb3 is selected as an alternate power pin, vddio, the power supply of all the pins on this port, except pb3, together with pc4 can be selected individually to come from the vdd pin or from vddio by configuration options. rev. 1.00 10 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
pin name i/o configuration option description pc0/osc1 pc1/osc2 pc2/osc3 pc3/osc4 pc4/pwm0/scs0 pc5/pwm1/pclk pc6/pwm2/pint i/o erc or hirc or ec 32.768khz sim0 vddio bidirectional 7-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a pull-high resistor can be connected to each pin determined by the pcpu register. osc1 and osc2 are connected to an external rc network or crystal, determined by configuration options, for the internal system clock. if the rc system clock option is selected, the osc2 pin can be used as an i/o pin. the internal system can come from the internal high speed rc oscillator (hirc) selected by configuration options. when the hirc is selected as the system oscillator, the osc1 and osc2 pins can be used as normal i/o pins. the abbreviation ec stands for external clock mode. in the ec mode, an external clock source is provided on osc1 as the system clock. osc3 and osc4 are connected to a 32.768khz crystal oscillator to form a clock source for f sub or f sl . pwm0, pwm1 and pwm2 are pin-shared with pc4, pc5 and pc6 respectively. pc4 is also pin-shared with scs0 , the chip select pin for the serial interface module 0. the power supply to pc4 can be selected to come from vdd or vddio determined by a configuration option. the pclk is a peripheral clock output pin which is enabled by the pcken in the sim0ctrl register and pin-shared with pc5. the pint is the external peripheral interrupt pin and pin-shared with pc6. pc7/res i/o res schmitt trigger reset input pin, active low. the res pin is pin-shared with pc7 whose function is determined by a configuration option. when pc7 is configured as an i/o pin, software instructions determine if this pin is an open drain output or a schmitt trigger input without pull-high resistor. lcd vlcd p lcd power supply com15/seg80 com14/seg81 com13/seg82 com12/seg83 com11/seg84 com10/seg85 com9/seg86 com8/seg87 o com15~com8 are lcd driver outputs for lcd panel commons while seg80~seg87 are lcd driver outputs for lcd panel segments. these pins can be configured as segments or common lcd driver outputs by related lcd control bits. com7~com0 o lcd driver outputs for lcd panel commons. seg79~seg24 lcd driver outputs for lcd panel segments. seg23~seg16/ pf7~pf0 i/o lcd driver outputs for lcd panel segments. seg23~seg16 can be set as segment outputs or logic i/o pins by the lcd output control register lcdio. seg15~seg8/ pe7~pe0 i/o lcd driver outputs for lcd panel segments. seg15~seg8 can be set as segment outputs or logic i/o pins by the lcd output control register lcdio. seg7~seg0/ pd7~pd0 i/o lcd driver outputs for lcd panel segments. seg7~seg0 can be set as segment outputs or logical i/o pins by the lcd output control register lcdio. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 11 december 2, 2011
pin name i/o configuration option description power & ground vdd p positive power supply vss p negative power supply, ground avdd p analog positive power supply avss p analog negative power supply, ground cvss p dc/dc converter negative power supply, ground usb dp i/o usb d+ line dm i/o usb d- line v33o p usb 3.3v regulator output iso 7816 - smart card interface vo p external diode connection pin for dc/dc converter self p external inductor connection pin for dc/dc converter crst o smart card reset output cclk o smart card clock output cc4 i/o smart card c4 input/output cc8 i/o smart card c8 input/output cio i/o smart card data input/output cdet i smart card detection input crdvcc p positive power supply for external smart card note: * for proper operation, v ddio v dd absolute maximum ratings supply voltage ...............................................................................................v ss 0.3v to v ss +6.0v storage temperature ................................................................................................. 50 cto125 c input voltage .................................................................................................v ss 0.3v to v dd +0.3v operating temperature................................................................................................ 40 cto85 c i ol total.......................................................................................................................... ...........80ma i oh total .................................................................................................................................. 80ma total power dissipation .........................................................................................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum rat - ings may cause substantial damage to the device. functional operation of this device at other condi - tions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. rev. 1.00 12 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =12mhz 3.0 5.5 v f sys =20mhz 4.5 5.5 v operating current i dd1 operating current (hxt, erc osc) 3v no load, f sys =f m =1mhz 170 250 a 5v 380 570 a i dd2 operating current (hxt, erc osc) 3v no load, f sys =f m =2mhz 240 360 a 5v 490 730 a i dd3 operating current (hxt, erc, hirc osc) 3v no load, f sys =f m =4mhz (note 5) 440 660 a 5v 900 1450 a i dd4 operating current (ec mode) 3v no load, f sys =f m =4mhz 380 570 a 5v 680 1020 a i dd5 operating current (hxt, erc osc) 3v no load, f sys =f m =6mhz 700 1050 a 5v 1300 1950 a i dd6 operating current (hxt, erc, hirc osc) 5v no load, f sys =f m =8mhz 1.8 2.7 ma i dd7 operating current (hxt, erc, hirc osc) 5v no load, f sys =f m =12mhz 2.6 4.5 ma i dd8 operating current (slow mode, f m =4mhz) (crystal, erc, hirc osc) 3v no load, f sys =f slow =500khz 150 220 a 5v 340 510 a i dd9 operating current (slow mode, f m =4mhz) (hxt, erc, hirc osc) 3v no load, f sys =f slow =1mhz 180 270 a 5v 400 600 a i dd10 operating current (slow mode, f m =4mhz) (hxt, erc, hirc osc) 3v no load, f sys =f slow =2mhz 270 400 a 5v 560 840 a i dd11 operating current (slow mode, f m =8mhz) (hxt, erc, hirc osc) 3v no load, f sys =f slow =1mhz 240 360 a 5v 540 810 a i dd12 operating current (slow mode, f m =8mhz) (hxt, erc, hirc osc) 3v no load, f sys =f slow =2mhz 320 480 a 5v 680 1020 a i dd13 operating current (slow mode, f m =8mhz) (hxt, erc, hirc osc) 3v no load, f sys =f slow =4mhz 500 750 a 5v 1000 1500 a i dd14 operating current (f sys = % lxt or lirc) 3v & lcd on, 1/5 bias (r bias =1m
), v lcd =v dd 10 20 a 5v 20 40 a HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 13 december 2, 2011
symbol parameter test conditions min. typ. max. unit v dd conditions i dd15 operating current (f sys = % lxt or lirc) 3v & lcd on, 1/4 bias (r bias =800k
), v lcd =v dd 15 25 a 5v 25 40 a i dd16 operating current (f sys = % lxt or lirc) 3v & lcd on, 1/3 bias (r bias =600k
), v lcd =v dd 15 25 a 5v 25 40 a i dd17 operating current (f sys = % lxt or lirc) 3v lcd off, wdt off 816 a 5v 15 30 a i dd18 operating current (f sys = % lxt or lirc) 3v & lcd on, 1/5 bias (r bias =100k
), v lcd =v dd 40 60 a 5v 70 110 a i dd19 operating current (f sys = % lxt or lirc) 3v & lcd on, 1/4 bias (r bias =80k
), v lcd =v dd 50 75 a 5v 80 120 a i dd20 operating current (f sys = % lxt or lirc) 3v & lcd on, 1/3 bias (r bias =60k
), v lcd =v dd 70 110 a 5v 100 150 a standby current i stb1 standby current (sleep) (f sys ,f sub ,f s ,f lcd ,f wdt =off) 3v system halt, lcd off, wdt off, dc/dc converter off 0.2 1.0 a 5v 0.3 2.0 a i stb2 standby current (sleep) (f sys ,f lcd off, f wdt =f sub = % lxt or lirc 3v system halt, lcd off, wdt on, dc/dc converter off 24 a 5v 35 a i stb3 standby current ( idle) (f sys ,f wdt =off; *f s =f sub = % lxt or lirc) 3v system halt, wdt off, & lcd on, 1/5 bias, dc/dc converter off, (r bias =1m
), v lcd =v dd 610 a 5v 10 15 a i stb4 standby current (idle) (f sys ,f wdt =off; *f s =f sub = % lxt or lirc) 3v system halt, wdt off, & lcd on, 1/4 bias, dc/dc converter off, (r bias =800k
), v lcd =v dd 610 a 5v 10 15 a i stb5 standby current (idle) (f sys ,f wdt =off; *f s =f sub = % lxt or lirc) 3v system halt, wdt off, & lcd on, 1/3 bias, dc/dc converter off, (r bias =600k
), v lcd =v dd 812 a 5v 12 16 a i stb6 standby current (idle) (f sys ,f wdt =off; *f s =f sub = % lxt or lirc) 3v system halt, wdt off, & lcd on, 1/5 bias, dc/dc converter off, (r bias =100k
), v lcd =v dd 26 39 a 5v 44 66 a i stb7 standby current (idle) (f sys ,f wdt =off; *f s =f sub = % lxt or lirc) 5v system halt, wdt off, & lcd on, 1/4 bias, dc/dc converter off, (r bias =80k
), v lcd =v dd 32 48 a 5v 54 81 a i stb8 standby current (idle) (f sys ,f wdt =off; *f s =f sub = % lxt or lirc) 3v system halt, wdt off, & lcd on, 1/3 bias, dc/dc converter off, (r bias =60k
), v lcd =v dd 44 66 a 5v 70 105 a rev. 1.00 14 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
symbol parameter test conditions min. typ. max. unit v dd conditions i stb9 standby current (idle), (f sys =on, f sys =f m =4mhz, f wdt ,f lcd =off, *f s =f sub = % lxt or lirc) 3v system halt, wdt off, lcd off, spi or i 2 c on, pclk on, pclk=f sys /8 150 250 a 5v 350 550 a f sys standby current (sleep) (f sys ,f sub ,f s ,f lcs ,f wdt =off) 5v system halt, lcd off, wdt off, dc/dc converter off 0.1 1.2 a input high/low voltage v il1 input low voltage for i/o ports, tmr and int pins 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr and int pins 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v sink/source current i ol1 i/o sink current (pa, pb, pc; seg, com level or led output) 3v v ol =0.1v dd 612 ma 5v 10 25 ma i oh1 i/o source current (pa, pb, pc; seg, com level or led output) 3v v oh =0.9v dd 2 4 ma 5v 5 8 ma i ol2 lcd common and segment current 3v v ol =0.1v dd 210 420 a 5v 350 700 a i oh2 lcd common and segment current 3v v oh =0.9v dd 80 160 a 5v 180 360 a i ol3 pc7/res sink current 5v v ol =0.1v dd 23 ma i ol4 card clock (cclk) sink current 3v v ol =0.1v dd 40 a 5v 60 a i oh4 card clock (cclk) source current 3v v oh =0.9v dd 40 a 5v 60 a i ol5 card i/o (cio) sink current 3v v ol =0.1v dd 400 a 5v 600 a i oh5 card i/o (cio) source current 3v v oh =0.9v dd 15 a 5v 15 a i ol6 card reset (crst), c4/c8 sink current 3v v ol =0.1v dd 400 a 5v 600 a i oh6 card reset (crst), c4/c8 source current 3v v oh =0.9v dd 15 a 5v 15 a HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 15 december 2, 2011
symbol parameter test conditions min. typ. max. unit v dd conditions pull-high resistance r ph1 pull-high resistance for general i/o ports & card detection (cdet) 3v 40 60 80 k
5v 10 30 50 k
r ph2 pull-high resistance for card i/o (cio) $ 7.5 15.0 22.5 k
lvr/lvd v lvr low voltage reset voltage configuration option: 2.1v 1.98 2.10 2.22 v configuration option: 3.15v 2.98 3.15 3.32 v configuration option: 4.2v 3.98 4.20 4.42 v v lvd low voltage detector voltage configuration option: 2.2v 2.08 2.20 2.32 v configuration option: 3.3v 3.12 3.30 3.50 v configuration option: 4.4v 4.12 4.40 4.70 v v 33o usb 3.3v regulator output 5v i v33o =-5ma 3.0 3.3 3.6 v v bg bandgap reference with buffer voltage -3% typ. tbd +3% typ. v note: 1. * f s is the internal clock for the buzzer, rtc, time base and wdt. 2. % lxt in slow start mode (rtcc.4=1) for d.c. current measurement. 3. lxt = 32768 crystal and lirc = internal 32k rc oscillator. 4. & lcd waveform is in type a condition. 5. timer0/1 off. timer filter is disabled for all test conditions. a.c. characteristics symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal, erc, hirc osc) 2.2v~5.5v 400 4000 khz 3.0v~5.5v 400 12000 khz 4.5v~5.5v 400 20000 khz f sys2 system clock (lxt osc) 2.2v~5.5v 32768 hz f lxt lxt frequency 32768 hz f 4merc 4mhz external rc osc 5v r=150k
2% 4 2% mhz 2.2v~ 5.5v r=150k
, ta=0 c~70 c 7% 4 7% mhz r=150k
, ta=-40 c~85 c 11% 4 11% mhz rev. 1.00 16 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
symbol parameter test conditions min. typ. max. unit v dd conditions f hirc 4/8/12mhz internal rc osc 3v/5v ta=25 c 2% 4 +2% mhz 3v/5v ta=25 c 2% 8 +2% mhz 5v ta=25 c 2% 12 +2% mhz 3v/5v ta=0~70 c 5% 4 +5% mhz 3v/5v ta=0~70 c 5% 8 +5% mhz 5v ta=0~70 c 5% 12 +5% mhz 2.2v~ 5.5v ta=0~70 c 8% 4 +8% mhz 3.0v~ 5.5v ta=0~70 c 8% 8 +8% mhz 4.5v~ 5.5v ta=0~70 c 8% 12 +8% mhz 2.2v~ 5.5v ta= 40 c~85 c 12% 4 +12% mhz 3.0v~ 5.5v ta= 40 c~85 c 12% 8 +12% mhz 4.5v~ 5.5v ta= 40 c~85 c 12% 12 +12% mhz f timer timer i/p frequency (tmr0/tmr1/tmr2/tmr3) 2.2v~5.5v 0 4000 khz 3.0v~5.5v 0 8000 khz 4.5v~5.5v 0 12000 khz f lirc 32k rc frequency 2.2v~ 5.5v after trim 28.1 32.0 34.4 khz t res external reset low pulse width 1 s t lvr low voltage width to reset 0.1 0.4 0.6 ms t lvds lvd output stable time lvr disable, lvd enable, bandgap voltage ready 100 s t sst1 system start-up timer period (without fast start-up) for hxt/lxt power up or wake-up from halt 1024 t sys t sst2 system start-up timer period (with fast start-up) for hxt/lxt wake-up from idle mode (f sl =f lxt ) 12 t lxt % t sst3 system start-up timer period (with fast start-up) for hxt/lxt wake-up from idle mode (f sl =f lirc ) 12 t lirc * t int interrupt pulse width 1 s note: *t sys =1/f sys %: t lxt is period of 32768 xtal *: t lirc is period of internal 32k rc HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 17 december 2, 2011
a/d converter characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions av dd analog operating voltage v ref =av dd 2.7 5.5 v v ad a/d input voltage 144-pin lqfp 0 v ref v v ref a/d input reference voltage range av dd =5v 2.0 av dd +0.1 v dnl a/c differential non-linearity av dd =5v, v ref =av dd , t ad =0.5s 2 2 lsb inl adc integral non-linearity av dd =5v, v ref =av dd , t ad =0.5s 4 4 lsb i adc additional power consumption if a/d converter is used 3v 0.50 0.75 ma 5v 1.00 1.50 ma t ad a/d converter clock period 0.5 10 s t adc a/d conversion time (include sample and hold time) 12-bit a/d converter 16 t ad t ads a/d sampling time 4 t ad t on2st a/d on to a/d start 2.7v~5.5v 2 s note: adc conversion time (t adc ) = n (bits adc) + 4 (sampling time). the conversion for each bit needs one adc clock (t ad ). power-on reset characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions i por dc operating current 2.2v~ 5.5v ta=25 c 0.7 a v por vdd start voltage to ensure power-on reset 100 mv rr vdd vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms rev. 1.00 18 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
4 ' ' 4 4 ' '
dc/dc converter and ldo electrical characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions dc/dc v in dc/dc input voltage 2.5 5.5 v vo1 dc/dc dc/dc output voltage 1 3.610 3.800 3.990 v vo2 dc/dc dc/dc output voltage 2 4.750 5.500 5.775 v efficiency v in =5v, v o =5.5v, iv dd =100ma, i out =55ma, i usb =15ma (reception mode), cpu in idle mode 70 % i vdd vdd supply current 100 ma 5v regulator output v in dc/dc input voltage 3.6 5.5 v v crdvcc smart card power supply voltage 4.6 5.0 5.4 v i sc smart card supply current 55 ma i ovdet current overload detection 70 95 150 ma i qui quiescent current v o =5.5v, v crdvcc =5v, c load =4.7f, no load current 100 150 a t idet detection time on current overload 170 1400 s t off v crdvcc turn off time 4.6v~ 5.4v c load 4.7f, card voltage=v crdvcc to 0.4v 750 s t on v crdvcc turn on time 4.6v~ 5.4v c load 4.7f, card voltage= 0v to v crdvcc (min.) 750 s v5 pwrgood ldo 5v power good voltage 4.8 v v5 ripple ripple on card voltage 200 mv HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 19 december 2, 2011
symbol parameter test conditions min. typ. max. unit v dd conditions 3v regulator output v in dc/dc input voltage 2.50 5.50 v v crdvcc smart card power supply voltage 2.76 3.00 3.24 v i sc smart card supply current 50 ma i ovdet current overload detection 70 95 120 ma t idet detection time on current overload 170 1400 s t off v crdvcc turn off time 4.6v~ 5.4v c load 4.7f, card voltage=v crdvcc to 0.4v 750 s t on v crdvcc turn on time 4.6v~ 5.4v c load 4.7f, card voltage= 0v to v crdvcc (min.) 750 s v3 pwrgood ldo 3v power good voltage 2.88 v v3 ripple ripple on card voltage 200 mv 1.8v regulator output v in dc/dc input voltage 2.50 5.50 v v crdvcc smart card power supply voltage 1.656 1.800 1.944 v i sc smart card supply current 20 ma i ovdet current overload detection 70 95 12 ma t idet detection time on current overload 170 1400 s t off v crdvcc turn off time 4.6v~ 5.4v c load 4.7f, card voltage=v crdvcc to 0.4v 750 s t on v crdvcc turn on time 4.6v~ 5.4v c load 4.7f, card voltage= 0v to v crdvcc (min.) 750 s v18 pwrgood ldo 1.8v power good voltage 1.73 v rev. 1.00 20 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a crystal/resonator or rc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontrollers ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. when the external rc oscillator is used, osc2 is free for use as a nomral i/o pin. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 21 december 2, 2011 5 , @ a ! " , @ : a 5 , @ b : a ! " , @ a 5 , @ b + a ! " , @ b : a b : b +
/ @ / a / : / + / * / 7

system clocking and pipelining 5 , : ! " , : 5 , + 5

: + * 7 8 . ' ! % $ c d 4 $ e f : + 0 g $ % % ' ! % $ c % f : + 0 g d d 6 ! " , + 5 , * 5 , . ! " , . 5 , - instruction fetching
for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontrollers manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. rev. 1.00 22 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces mode program counter bits b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 0 00000 0000000000 smart card interrupt 000000 0000000100 usb interrupt 000000 0000001000 external interrupt 0 0 00000 0000001100 external interrupt 1 0 00000 0000010000 timer/event counter 1 overflow 0 00000 0000010100 timer/event counter 0 overflow 0 00000 0000011000 smart card insertion/removal interrupt 000000 0000011100 a/d converter interrupt 0 00000 0000100000 multi-function 0 interrupt 0 00000 0000100100 multi-function 1 interrupt 0 00000 0000101000 skip program counter+2 (within current bank) loading pcl pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch bp.7 bp.6 bp.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc15~pc8: current program counter bits @7~@0: pcl bits #12~#0: instruction code address bits s15~s0: stack register bits bp.7, bp.6, bp.5: bank pointer bits : * : + - 9 2 , 8 2 , . : 7 2 , - : 8
the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontrollers that carries out arithmetic and logic operations of the instruction set. connected to the main microcontrollers data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 23 december 2, 2011 / % ( : / % ( + / % ( * / % ( : + ) / /
2 ) /
program memory the program memory is the location where the user code or program is stored. for the device the program memory is an otp type, which means it can be programmed only one time. by using the appropriate programming tools, this otp memory device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming. structure the program memory has a capacity of 48k 16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt-entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. special vectors within the program memory, certain locations are reserved for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. location 004h this vector is used by the smart card interrupt. if a related smart card interrupt event occurs, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 008h this vector is used by the usb interrupt. if the related usb interrupt event occurs, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 00ch this vector is used by the external interrupt 0. if the related external interrupt pin receives an active edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 010h this vector is used by the external interrupt 1. if the related external interrupt pin receives an active edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 014h this internal vector is used by the timer/event counter 0. if a timer/event counter 0 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. location 018h this internal vector is used by the timer/event counter 1. if a timer/event counter 1 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. location 01ch this vector is used by the smart card insertion/removal interrupt. if a smart card insertion or removal event occurs, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. rev. 1.00 24 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
location 020h this vector is reserved for the a/d converter interrupt. if the completion of an a/d conversion occurs, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 024h this internal vector is used by the multi-function 0 interrupt. the multi-function 0 interrupt vector is shared by several internal functions such as a serial interface module 0 interrupt, an active edge appearing on the external peripheral interrupt pin, a time base overflow or a real time clock overflow. the program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. location 028h this internal vector is used by the multi-function 1 interrupt. the multi-function 1 interrupt vector is shared by several internal functions such as a serial interface module 1 interrupt, a timer/event counter 2 or a timer/event counter 3 overflow. the program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 25 december 2, 2011 9 : 7 0 9 9 9 0 9 9 7 0 9 9 0 9 9 0 9 : 9 0 9 : 0 6 2 5 5 5 0 : .

4 4 ! " 9 4
& ! ( 9 4 2 4 ! " : 4
& ! ( : 4 9 : 0 - 9 9 0 - 5 5 0 9 9 0 : 5 5 5 0 + 9 9 9 0 9 + 7 0 9 + 9 0 9 + 0
5
9 4 $ & ' (

4
5
: 4 9 + 0
& ( 4 program memory structure
look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, tblp. this register defines the lower 8-bit address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc[m] or tabrdl [m] instructions, respectively. when these instructions are executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0 . the following diagram illustrates the addressing/data flow of the look-up table: instruction table location bits b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 0 111111@7@6@5@4@3@2@1@0 table location note: pc15~pc8: current program counter bits @7~@0: table pointer tblp bits tbhp: table pointer higher-order byte bits. table program example the following example shows how the table pointer and table data is defined and retrieved from the HT56RB688. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is bf00h which refers to the start address of the last page within the 48k program memory of the HT56RB688 microcontroller. the table pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data table will be at the program memory address bf06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any rev. 1.00 26 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
2 % 0
0
2 % 3 2 % : 8 h 0
2 2 %
' $ : .
!
main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page mov a, 0bfh ; initialise high table pointer mov tbhp, a : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address bf06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address bf05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org bf00h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. divided into three sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 27 december 2, 2011 00h 7fh 80h ffh special purpose data memory general purpose data memory bank 0 bank 4 bank 31 bank 1 and bank 2 lcd memory bank 3 data memory structure
reserved for general purpose use. all locations within this area are read and write accessible under program control. the third area is reserved for the lcd memory. this special area of data memory is mapped directly to the lcd display so data written into this memory area will directly affect the displayed data. the addresses of the lcd memory area overlap those in the general purpose data memory area. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. data memory bank number 0 1 2 3~31 special purpose data memory start address common: 00h end address common: 7fh general purpose and lcd data memory start address 80h 80h 80h 80h end address ffh cfh cfh ffh data memory content structure the data memory is subdivided into several banks, all of which are implemented in 8-bit wide ram. the data memory located in bank 0 is subdivided into two sections, the special purpose data memory and the general purpose data memory. the start address of the data memory for the device is the address 00h . registers which are common to the microcontroller, such as acc, pcl, etc., have the same data memory address. the lcd memory is mapped into bank 1 and bank 2. banks 3 to 31 contain only general purpose data memory for the device with larger data memory capacities. as the special purpose data memory registers are mapped into all bank areas, they can subsequently be accessed from any bank location. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user program for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. for the device with larger data memory capacities, the general purpose data memory, in addition to being located in bank 0, is also stored in banks 3 to bank 31. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both read and write type but some are protected and are read only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the unknow value. the special function registers are mapped into all banks and can therefore be accessed from any bank location. display memory the data to be displayed on the lcd or led display is stored in an area of fully accessible data memory. by writing to this area of ram, the display output can be directly controlled by the application program. as this memory exists in bank 1 and bank 2, but have addresses which map into the general purpose data memory, it is necessary to first ensure that the bank pointer is set to the value 01h or 02h before accessing the display memory. the display memory can only be accessed indirectly using the memory rev. 1.00 28 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
pointer mp1 and the indirect addressing register iar1. when the bank pointer is set to 01h or 02h to select data memory bank 1 or bank 2 to access the display memory, if any addresses with a value less than 80h are read, the special purpose data memory in bank 0 will be accessed. also, if the bank pointer is set to 01h or 02h to select data memory bank 1 or bank 2, if any addresses higher than the last address in bank 1 or bank 2 are read, then a value of 00h will be returned. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 29 december 2, 2011 9 9 0 9 : 0 9 + 0 9 * 0 9 7 0 9 8 0 9 . 0 9 - 0 9 0 9 = 0 9 $ 0 9 2 0 9 0 9 ' 0 9 ! 0 9 5 0 : 9 0 : : 0 : + 0 : * 0 : 7 0 : 8 0 : . 0 : - 0 : 0 : = 0 : $ 0 : 2 0 : 0 : ' 0 : ! 0 : 5 0 + 9 0 + : 0 + + 0 + * 0 + 7 0 + 8 0 + . 0 + - 0 + 0 + = 0 + $ 0 + 2 0 + 0 + ' 0 + ! 0 + 5 0 * 9 0 * : 0 * + 0 * * 0 * 7 0 * 8 0 * . 0 * - 0 * 0 * = 0 * $ 0 * 2 0 * 0 * ' 0 * ! 0 * 5 0 $ 9 9 $ : : 2 $ % 2 % 2 % 0 $ 2 0 9 : % ; ' ' + ' 6 9 6 : 6 + 5 9 5 : $ $ $ $ 2 2 2 ' ' ' ! ! ! 5 5 5 9 % 9 0 : % : 0 + % + 0 * % * 0 9 9 : 0 : % : + + * * % ! ' % % ' % % ' 5 % $ ' % $ ' 0 $ ' $ $ ' 9 % 9 9 % : 9 ' 9 $ & 9 % + : % 9 : % : : ' : $ & : % + ' $ % ' $ 0 ' $ % ! : ! 9 < : < 9 + : 9 ! # 2 # 2 $ $ % % ! ! 5 5 9 5 5 : 5 5 + 5 5 * 5 5 7 5 5 8 6 ! 7 9 0 7 : 0 7 + 0 7 * 0 7 7 0 7 8 0 7 . 0 7 - 0 7 0 7 = 0 7 $ 0 7 2 0 7 0 7 ' 0 7 ! 0 7 5 0 8 9 0 8 : 0 8 + 0 8 * 0 8 7 0 8 8 0 8 . 0 8 - 0 8 0 8 = 0 8 $ 0 8 2 0 8 0 8 ' 0 8 ! 0 8 5 0 . 9 0 . : 0 . + 0 . * 0 . 7 0 . 8 0 . . 0 . - 0 . 0 . = 0 . $ 0 . 2 0 . 0 . ' 0 . ! 0 . 5 0 - 9 0 - : 0 - + 0 - * 0 - 7 0 - 8 0 - . 0 - - 0 - 0 - = 0 - $ 0 - 2 0 - 0 - ' 0 - ! 0 - 5 0 d i # # i special purpose data memory
special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control and a/d converter operation. the location of these registers within the data memory begins at the address 00h . any unused data memory locations between these special function registers and the point where the general purpose memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a unknow value. indirect addressing registers iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks. the following example shows how to clear a section of four ram locations already defined as locations adres1 to adres4. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. rev. 1.00 30 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
bank pointer bp the data memory is divided into a total of 32 banks. selecting the required data memory area is achieved using the bank pointer. if data in bank 0 is to be accessed, then the bp register must be loaded with the value 00h, while if data in bank 1 is to be accessed, then the bp register must be loaded with the value 01h, and so on. the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. bit76543210 name bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~5 bp7~bp5 : program memory bank selection bits 000: program memory bank 0 001: program memory bank 1 010: program memory bank 2 011: program memory bank 3 100: program memory bank 4 101: program memory bank 5 110~111: not implemented | the program memory has the capacity of 48k words implemented as 8k words 6 banks. bit 4~0 bp4~bp0 : data memory bank selection bits 00000: bank 0 for general purpose data memory 00001: bank 1 for lcd display memory 00010: bank 2 for lcd display memory 00011~ 11111: bank 3 ~ bank 31 for general purpose data memory accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specified program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 31 december 2, 2011
look-up table registers tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp registers are the lower order byte and high order byte table pointers and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defined location. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, operations related to the status register may give different results due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. bit76543210 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 00xxxx x unknown bit 7, 6 unimplemented, read as 0 bit 5 to : watchdog time-out flag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down flag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. rev. 1.00 32 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
interrupt control registers these 8-bit registers, known as intc0, intc1, intc2, mfic0, mfic1 and misc0, control the overall operations of the device interrupt functions. by setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. a master interrupt bit within the intc0 register, the emi bit, acts like a global enable/disable control and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt subroutine is entered to disable further interrupt and is set by executing the reti instruction. the misc0 register is used to select the active edges for the two external interrupt pins int0 and int1. timer/event counter registers the device contains several internal 8-bit and 16-bit timer/event counters. the registers tmr0, tmr2, tmr3 and the register pair tmr1l/tmr1h are the locations where the timer values are located. these registers can also be preloaded with fixed data to allow different time intervals to be setup. the associated control registers, tmr0c, tmr1c, tmr2c and tmr3c contain the setup information for these timers, which determines in what mode the timer is to be used as well as containing the timer on/off control function. input/output ports and control registers within the area of special function registers, the i/o data registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb, pc, pd, pe and pf. these labeled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc, pcc, pdc, pec and pfc also mapped to specific addresses within the data memory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high while for an output it must be set low. during program initialization, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits using the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipulating specific bits of the i/o control registers during normal program operation is a useful feature of these devices. pulse width modulator registers the device contains multiple pulse width modulator outputs each with their own related independent control register pair, known as pwm0l/pwm0h, pwm1l/pwm1h, pwm2l/pwm2h and pwm3l/pwm3h. the 12-bit contents of each register pair, which defines the duty cycle value for the modulation cycle of the pulse width modulator, along with an enable bit are contained in these register pairs. a/d converter registers adrl, adrh, adcr, acsr the device contains a multiple channel 12-bit a/d converter. the correct operation of the a/d requires the use of two data registers and two control registers. the two data registers, a high byte data register known as adrh, and a low byte data register known as adrl, are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. functions such as the a/d enable/disable, a/d channel selection and a/d clock frequency are determined using the two control registers, adcr and acsr. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 33 december 2, 2011
serial interface module registers the device contains two serial interface modules named sim0 and sim1 and each sim contains an spi and an i 2 c interface. the simxctl0, simxctl1, simxctl2 and simxar are the control registers for the serial interface function while the simxdr is the data register for the serial interface data where x means 0 and 1. port a wake-up register pawu all pins on port a have a wake-up function enable a low going edge on these pins to wake-up the device when it is in a power down mode. the pins on port a that are used to have a wake-up function are selected using this resister. pull-high registers papu, pbpu, pcpu, pdpu, pepu, pfpu all i/o pins on ports pa, pb, pc, pe, pe and pf if setup as inputs, can be connected to an internal pull-high resistor. the pins which require a pull-high resistor to be connected are selected using these registers. clock control register clkmod the device operates using a dual clock system whose mode is controlled using this register. the register controls functions such as the clock source, the idle mode enable and the division ratio for the slow clock. lcd/led registers lcdctrl, ledctrl, lcdio the device contains a fully integrated lcd/led driver function which can be setup in various configurations allowing it to control a wide range of external lcd and led panels. most of these options are controlled using the lcdctrl and lectrl registers. as some of the lcd segment driving pins, which are pin-shared with i/o pins, can also be setup to be used as general i/o pins, the register named lcdio is used to select the required function. miscellaneous register misc0, misc1 these registers name misc0 and misc1 are used to control the miscellaneous functions such as the active edge selection of the external interrupt pins, the clock divided ratio selection of the smart card and the watchdog timer enable control bits. there are also four bits used to determine if the output type is open drain or cmos output for pa0~pa3. input/output ports holtek microcontroller offer considerable flexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides up to 48 bidirectional input/output lines labeled with port names pa, pb, pc, pd, pe and pf. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. rev. 1.00 34 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu, pbpu, pcpu, pdpu, pepu and pfpu and are implemented using weak pmos transistors. pawu, papu, pa, pac, pbpu, pb, pbc, pcpu, pc, pcc, pdpu, pd, pdc, pepu, pe, pec, pfpu, pf and pfc registers register name por bit 76543210 pawu 00h pawu7 pawu6 pawu5 pawu4 pawu3 pawu2 pawu1 pawu0 pa ffh pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pac ffh pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 papu 00h papu7 papu6 papu5 papu4 papu3 papu2 papu1 papu0 pb ffh pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pbc ffh pbc7 pbc6 pbc5 pbc4 pbc3 pbc2 pbc1 pbc0 pbpu 00h pbpu7 pbpu6 pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pc ffh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pcc ffh pcc7 pcc6 pcc5 pcc4 pcc3 pcc2 pcc1 pcc0 pcpu 00h pcpu7 pcpu6 pcpu5 pcpu4 pcpu3 pcpu2 pcpu1 pcpu0 pd ffh pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pdc ffh pdc7 pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 pdpu 00h pdpu7 pdpu6 pdpu5 pdpu4 pdpu3 pdpu2 pdpu1 pdpu0 pe ffh pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pec ffh pec7 pec6 pec5 pec4 pec3 pec2 pec1 pec0 pepu 00h pepu7 pepu6 pepu5 pepu4 pepu3 pepu2 pepu1 pepu0 pf ffh pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 pfc ffh pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 pfpu 00h pfpu7 pfpu6 pfpu5 pfpu4 pfpu3 pfpu2 pfpu1 pfpu0 pawun : pa wake-up function enable 0: disable 1: enable papun/pbpun/pcpun/pdpun/pepun/pfpun : pull-high function enable 0: disable 1: enable pan/pbn/pcn/pdn/pen/pfn : i/o port data bit pacn/pbcn/pccn/pdcn/pecn/pfcn : i/o port type selection bit 0: output 1: input port a wake-up the halt instruction forces the microcontroller into a power down condition which preserves power, a feature that is important for battery and otuher low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. after a halt instruction forces the microcontroller into entering a power down condition, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 35 december 2, 2011
port a open drain function all i/o pins in the device have cmos structures, however port a pins pa0~pa3 can also be setup as open drain structures. this is implemented using the ode0~ ode3 bits in the misc1 register. misc1 register bit76543210 name ode3 ode2 ode1 ode0 wdten3 wdten2 wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00001010 bit 7 ode3 : pa3 open drain control 0: disable 1: enable bit 6 ode2 : pa2 open drain control 0: disable 1: enable bit 5 ode1 : pa1 open drain control 0: disable 1: enable bit 4 ode0 : pa0 open drain control 0: disable 1: enable bit 3~0 wdten3, wdten2, wdten1, wdten0 : wdt function enable described in watchdog timer section. i/o port control registers each i/o port has its own control register known as pac, pbc, etc., to control the input/output configuration. with this control register, each cmos output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. rev. 1.00 36 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
pin-shared functions the flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application program control. external interrupt inputs the external interrupt pins int0 and int1 are pin-shared with the i/o pins pa0 and pa1. for applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal i/o pin, however to do this, the external interrupt enable bits in the intc0 register must be disabled. external timer clock input the external timer pins tmr0, tmr1, tmr2 and tmr3 are pin-shared with i/o pins. to configure them to operate as timer inputs, the corresponding control bits in the timer control register must be correctly set and the pin must also be setup as an input. note that the original i/o function will remain even if the pin is setup to be used as an external timer input. pfd output the device contains a pfd function whose single output is pin-shared with i/o pin pa3. the output function of this pin is chosen via a configuration option and remains fixed after the device is programmed. note that the corresponding bit of the port control register, pac.3, must setup the pin as an output to enable the pfd output. if the pac port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the pfd configuration option has been selected. pwm outputs the device contains several pwm outputs name pwm0~pwm3 shared with pins pc4~pc6 and pa5. the pwm output functions are chosen via registers. note that the corresponding bit of the port control register bit must setup the pin as an output to enable the pwm output. if the port control register bit has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the pwm registers have enabled the pwm function. a/d inputs the device contains a multi-channel a/d converter inputs. all of these analog inputs are pin-shared with i/o pins on port a. if these pins are to be used as a/d inputs and not as normal i/o pins then the corresponding bits in the a/d converter control register, adcr, must be properly set. there are no configuration options associated with the a/d function. if used as i/o pins, then full pull-high resistor register remain, however if used as a/d inputs then any pull-high resistor selections associated with these pins will be automatically disconnected. i/o pin structures the accompanying diagrams illustrate the internal structures of some i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 37 december 2, 2011
rev. 1.00 38 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces 4 ' ' # / / '
' j ; ' j ; 2
' 2

'
' 2
&
j j $ / 0

generic input/output structure 4 ' ' # '
2
' 2

'
' 2
$ & ' $ + h $ 9 $ & ' ( + : 9 / $ ' j ; j ' j ; j 0

a/d input/output structure
programming considerations within the user program, one of the first things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac, pbc, etc., are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa, pb, etc., are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. lcd and led driver for large volume applications, which incorporate an lcd in their design, the use of a custom display rather than a more expensive character based display reduces costs significantly. however, the corresponding com and seg signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper lcd operation to occur. the device contains a lcd driver function, with their internal lcd signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom lcds. additionally the device also includes led driver circuitry which can generated the required signals to drive the com and segment signals for led panels. the device includes a wide range of options to enable lcd and led displays of various types to be driven. the table shows the range of options available across the device range. duty driver no. bias bias type wave type 1 / 8 888 1 / 3, 1 / 4, 1 / 5 ra , b 1 / 16 8016 lcd selections led duty led driver no. static 881 1 / 4 884 1 / 8 888 1 / 12 8012 1 / 16 8016 led selections HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 39 december 2, 2011 : + * 7 : + * 7
) / ' read/write timing
display memory an area of data memory is especially reserved for use for the lcd/led display data. this data area is known as the display memory. any data written here will be automatically read by the internal display driver circuits, which will in turn automatically generate the necessary lcd or led driving signals. therefore any data written into this memory will be immediately reflected into the actual display connected to the microcontroller. as the display memory addresses overlap those of the general purpose data memory, it s stored in its own independent bank 1 and bank 2 area. the data memory bank to be used is chosen by using the bank pointer, which is a special function register in the data memory named bp. to access the display memory therefore requires first that bank 1 or bank 2 is selected by writing a value of 01h or 02h to the bp register. after this, the memory can then be accessed by using indirect addressing through the use of memory pointer mp1. with bank 1 or bank 2 selected, then using mp1 to read or write to the memory area starting with address 80h will result in operations to the display memory. directly addressing the display memory is not applicable and will result in a data access to the bank 0 general purpose data memory. the accompanying display memory map diagrams shows how the internal display memory is mapped to the segments and commons of the display for the device. the accompanying waveform diagrams show the generated waveforms for a range of duty and bias types. the huge number of permutations of available for the lcd and led waveform types does not permit all types to be depicted. rev. 1.00 40 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces ! " # $ % 4 % ' 4 $ 4 2 % ' 3 4 @ k 4 % ' + & * a @ k 4 % ' : & * a @ k 4 % ' a % ' & ) ) ! " #
% ! " # % 4 % ' 4 $ 4 2 % ' 3 4 @ k 4 % ' 7 & 8 a @ k 4 % ' * & 8 a @ k 4 % ' a % ' & ) ) 4 % ' 4 $ 4 2 % ' 3 4 ' @ k 4 % ' * & 7 a @ k 4 % ' : & 7 a @ k 4 % ' a % ' & ) ) 4 @ k 4 % ' + & 7 a 4 ' 4 ! @ k 4 % ' + & 8 a @ k 4 % ' : & 8 a r type bias voltage levels
lcd/led registers control registers in the data memory, are used to control the various setup features of the lcd/led driver. there is one control register named lcdctrl for the lcd function and one named ledctrl for the led function. various bits in these registers control functions such as duty type, bias type, bias resistor selection as well as overall lcd enable and disable. the lcden bit in the lcdctrl and leden bit in the ledctrl register, which provide the overall lcd/led enable/disable function, will only be effective when the device is in the normal, slow or idle mode. if the device is in the sleep mode, the display will always be disabled. bits rsel0 and rsel1 in the lcdctrl register is used to select the internal bias resistors to supply the lcd panel with the correct bias voltages. a choice to best match the lcd panel used in the application can be selected also to minimise bias current. the type bit in the same register is used to select whether type a or type b lcd control signals are used. the register named lcdio is used to determine if the output function of display pins seg0~ seg23 are used as segment drivers or cmos outputs. if these pins are used as general i/o pins, then the i/o function including the input/output control, the related output data and pull-high functions is managed by the original corresponding i/o port control and data register together with the pull-high control register. lcd output control register lcdio bit76543210 name lcdpf lcdpe lcdpd r/w r/w r/w r/w por 000 bit 7~3 unimplemented, read as 0 bit 2 lcdpf : lcd seg16~seg23 or i/o port f selection bit 0: seg16~seg23 1: i/o port f bit 1 lcdpe : lcd seg8~seg15 or i/o port e selection bit 0: seg8~seg15 1: i/o port e bit 0 lcdpd : lcd seg0~seg7 or i/o port d selection bit 0: seg0~seg7 1: i/o port d lcd reset function the lcd has an internal reset function that is an or function of the inverted lcden bit in the lcdctrl register and the sleep function. the lcd reset signal is active high. the lcden signal is the inverse of the lcden bit in the lcdctrl register. reset lcd = sleep mode or lcden . leden = 0 and lcden = 1 must be enabled to activate the lcdctrl register function. lcden sleep mode reset lcd 0 off 0on 1 off x 1on lcd reset function HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 41 december 2, 2011
clock source the lcd clock source is the internal clock signal f sub divided by 8 using an internal divider circuit. the f sub internal clock is supplied by either the internal 32khz rc oscillator (lirc) or the external 32.768khz oscillator (lxt), the choice of which is determined by a configuration option. for proper lcd operation, this arrangement is provided to generate an ideal lcd clock source frequency of 4khz. f sub clock source lcd clock frequency internal 32khz oscillator (lirc) 4khz external 32.768khz oscillator (lxt) 4khz lcd clock source lcd driver output when the lcden bit in the lcdctrl register is set to 1, the com and seg lines will be setup as lcd driver pins to drive the lcd display. the number of com and seg outputs supplied by the lcd driver and its biasing and duty selections are dependent upon how the lcd control bits are programmed. the bias type is r type and the bias resistor can be selected using the rsel1 and rsel0 bits in the lcdctrl register. the nature of liquid crystal displays require that only ac voltages can be applied to their pixels as the application of dc voltages to lcd pixels may cause permanent damage. for this reason the relative contrast of an lcd display is controlled by the actual rms voltage applied to each pixel, which is equal to the rms value of the voltage on the com pin minus the voltage applied to the seg pin. this differential rms voltage must be greater than the lcd saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. the requirement to limit the dc voltage to zero and to control as many pixels as possible with a minimum number of connections requires that both a time and amplitude signal is generated and applied to the application lcd. these time and amplitude varying signals are automatically generated by the lcd driver circuits in the microcontroller. what is known as the duty determines the number of common lines used, which are also known as backplanes or coms. the duty which is chosen by a control bit to have a value of 1/8 and 1 / 16 and which equates to a com number of 8 and 16 therefore defines the number of time divisions within each lcd signal frame. two types of signal generation are also provided, known as type a and type b, the required type is selected via the type bit in the lcdctrl register. type b offers lower frequency signals, however lower frequencies may introduce flickering and influence display clarity. lcd control register lcdctrl bit76543210 name type dtyc bias1 bias0 rsel1 rsel0 lcden r/w r/w r/w r/w r/w r/w r/w r/w por 0 000000 bit 7 type : lcd type selection bit 0: type a 1: type b bit 6 unimplemented, read as 0 bit 5 dtyc : lcd duty selection bit 0: 1/8 duty 1: 1/16 duty bit 4~3 bias1~bias0 : lcd bias selection bits 00: 1/3 bias 01: 1/4 bias 10: 1/5 bias 11: reserved rev. 1.00 42 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
bit 2~1 rsel1~rsel0 : lcd bias resistor selection bits for 1/3 bias: 0x: 600k
10: 60k
11: 3k
for 1/4 bias: 0x: 800k
10: 80k
11: 4k
for 1/5 bias: 0x: 1000k
10: 100k
11: 5k
bit 0 lcden : lcd function enable control 0: disable 1: enable in normal, slow or idle mode, the lcd function will be enabled or disabled according to that the lcden bit is 1 or 0. in sleep mode, the lcd function will always be disabled. led driver output the led driver uses the com and seg lines to drive the led display. the number of com and seg outputs supplied by the led driver and its biasing and duty selections, are dependent upon how the led control bits are programmed. when the leden bit in the ledctrl register is set high and the lcden bit in the lcdctrl register is cleared to 0, the com and seg lines will be setup as cmos output pins to drive the led display. the com and seg lines can be set to be either active high or active low using bits in the ledctrl register. this provides 4 different timing modes. these are com low active, seg low active; com low active, seg high active; com high active, seg low active; com high active, seg high active. the com and seg lines will have a reverse polarity when in the non-active state when the display is off. for the led driver there are a total of 5 different duty cycle selections which are static, 1 / 4, 1 / 8, 1 / 12 and 1 / 16. the frame rate of each duty cycle will be between 55hz and 75hz. led control register ledctrl bit76543210 name dtye2 dtye1 dtye0 segp comp leden r/w r/w r/w r/w r/w r/w por 000000 bit 7 unimplemented, read as 0 bit 6~4 dtye2~dtye0 : led duty selection bit 000: static 001: 1/4 duty 010: 1/8 duty 011: 1/8 duty 100: 1/12 duty 101: 1/12 duty 110: 1/16 duty 111: 1/16 duty bit 3 segp : segment polarity selection bit 0: low active 1: high active HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 43 december 2, 2011
bit 2 comp : common polarity selection bit 0: low active 1: high active bit 1 leden : led function enable control 0: disable 1: enable in normal, slow or idle mode, the led function will be enabled or disabled according to that the leden bit is 1 or 0. in sleep mode, the lcd function will always be disabled. bit 0 unimplemented, read as 0 lcd voltage source and biasing the time and amplitude varying signals generated by the lcd driver function require the generation of several voltage levels for their operation. the number of voltage levels used by the signal depends upon the value of the bias bits in the lcdctrl register. the device supports the r type biasing and the bias resistor can be selected via the rsel bits in the lcdctrl register. for the r type biasing an external lcd voltage source must be supplied on pin vlcd to generate the internal biasing voltages. the vlcd voltage could be the microcontroller power supply vdd or some other voltage source less than or equal to the vdd voltage. for the r type 1 / 3 bias selection, four voltage levels vss, va, vb and vc are utilised. the voltage va is equal to vlcd and vb is equal to vlcd 2 / 3 while vc is equal to vlcd 1 / 3. for the r type 1 / 4 bias selection, there are five voltage levels to be used. the difference of each bias voltage is 1 / 4 vlcd voltage. for 1 / 5 bias selection, the difference of each bias voltage is 1 / 5 vlcd. in addition to selecting the lcd bias level, several values of bias resistor can be chosen using bits in the lcdctrl register. different values of internal bias resistors can be selected using the rsel0 and resel1 bits in the lcdctrl register. this bias resistor along with the voltage on pin vlcd will determine the bias current. rev. 1.00 44 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces 4 4 ' ' 4 4 ' ' 9
3
( ! <
3
( 9
3
( ! <

( 9

( ! <
3
( 9

( ! <

( 4 4 ' ' 4 4 ' ' 4 4 ' ' 4 4 ' ' 4 4 ' ' 4 4 ' ' 9 : + * - led static mode normal operation 4 4 ' ' 4 4 ' ' 4 4 ' ' 9 : ! < led 1 / 4 duty, com high active, seg low active, display off
HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 45 december 2, 2011 9 0 5 0 - . 8 7 * + : 9 9 : + : 0 - . 8 7 * + : 9 ! < 9 ! < - ! < : ! < . ! 0 - . 8 7 * ! < 9 ! < - = ! < : ! < - 9 0 : 0 - 0 . 0 & 9 : + - . 8 7 * memory map 888 & 9 0 5 0 - . 8 7 * + : 9 9 : + : 0 - . 8 7 * + : 9 ! < 9 ! < - = = : 9 : : ! < : ! < - ! 0 - . 8 7 * : + : * : 7 : 8 ! < 9 ! < - = ! < : ! < - 9 0 : 0 5 0 ! 0 memory map 8016
programming considerations certain precautions must be taken when programming the lcd/led. one of these is to ensure that the display memory is properly initialised after the microcontroller is powered on. like the general purpose data memory, the contents of the display memory are in an unknown condition after power-on. as the contents of the display memory will be mapped into the actual display, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. consideration must also be given to the capacitive load of the actual lcd used in the application. as the load presented to the microcontroller by lcd pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the com lines which may be connected to many lcd pixels. the accompanying diagram depicts the equivalent circuit of the lcd. one additional consideration that must be taken into account is what happens when the microcontroller enters a power down condition. the lcden control bit in the lcdctrl or leden bit in the ledctrl register permits the display to be powered off to reduce power consumption. if this bit is zero, the driving signals to the display will cease, producing a blank display pattern but reducing any power consumption associated with the lcd. after power-on, note that as the lcden and leden bits will be cleared to zero, the display function will be disabled. the accompanying timing diagrams depict the display driver signals generated by the microcontroller for various values of duty and bias. the huge range of various permutations only permit a few types to be displayed here. rev. 1.00 46 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces 9 : + ! < 9 ! < : ! < + ! < lcd panel equivalent circuit
HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 47 december 2, 2011 9 : ! < 9 4 4 ' ' ! < : + * 9 : + * 9 : + * 4 4 ' ' 4 4 ' ' 4 4 ' ' 4 4 ' ' 4 4 ' ' led 1 / 4 duty, com high active, seg low active, normal operation
rev. 1.00 48 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces during reset or in power down mode all common outputs all segment outputs va vb vc vss va vb vc vss normal operation mode va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss com0 com1 com2 com3 1frame com4 com5 com6 com7 com0 segments on com1 segments on com7 segments on com0 & com1 segments on va vb vc vss va vb vc vss com0 & com2 segments on com0 & com7 segments on all segments on lcd driver output type a, 1 / 8 duty, 1 / 3 bias
HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 49 december 2, 2011 during reset or in power down mode all common outputs all segment outputs va vb vc vss va vb vc vss normal operation mode va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss com0 com1 com2 com3 1frame com4 com5 com6 com7 com0 segments on com1 segments on com7 segments on com0 & com1 segments on va vb vc vss va vb vc vss com0 & com2 segments on com0 & com7 segments on all segments on lcd driver output type b, 1 / 8 duty, 1 / 3 bias
timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the device contains several 8-bit and 16-bit count-up timers. as each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. the provision of a prescaler to the clock circuitry of the 8-bit timer/event counter also gives added range to this timer. there are two types of registers related to the timer/event counters. the first are the registers that contain the actual value of the timer/event counter and into which an initial value can be preloaded. reading from these registers retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defines the timer options and determines how the timer/event counter is to be used. the timer/event counters can have their clock configured to come from an internal clock source. in addition, their clock source can also be configured to come from an external timer pin. rev. 1.00 50 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
& ! ( 6

& ! ( ' 2 ( ) 3 + - + h 9 @ : & : h : & : + a

& ! ( : 9 ) c 5 ' 9 ! 5
5 % @ 5
& ) ) a 8-bit timer/event counter structure !
& ! ( : . 2

' 2 ( ) 3 % 3 2 2 ) ) : 9 6 0
2 % 3 2 : .

& ! ( 5 ' : + # ) c & 7 # ) 2 ! " * + - . 0 1 * + ; 6 )

5
5 % @ 5
& ) ) a 16-bit timer/event counter structure # 5 ' 9 5 ' : )

5 '
configuring the timer/event counter input clock source the internal timer s clock can originate from various sources. the system clock source is used when the timer/event counter is in the timer mode or in the pulse width measurement mode. for the 8-bit timer/event counter this internal clock source is f sys which is also divided by a prescaler, the division ratio of which is conditioned by the timer control register, tmrnc, bits tnpsc0~ tnpsc2. for the 16-bit timer/event counter this internal clock source can be chosen from a combination of internal clocks using a configuration option and the tns bit in the tmrnc register. an external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin tmr0, tmr1, tmr2 or tmr3 depending upon which timer is used. depending upon the condition of the tne bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. name bits data register control register timer/event counter 0 8 tmr0 tmr0c timer/event counter 1 16 tmr1h/tmr1l tmr1c timer/event counter 2 8 tmr2 tmr2c timer/event counter 3 8 tmr3 tmr3c timer registers tmr0, tmr1l/tmr1h, tmr2, tmr3 the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. for the 8-bit timer/event counters, these registers are known as tmr0, tmr2 or tmr3. for the 16-bit timer/event counter, a pair of registers are required and are known as tmr1l/tmr1h. the value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh for the 8-bit timer or ffffh for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and continue counting. to achieve a maximum full range count of ffh for the 8-bit timer or ffffh for the 16-bit timer, the preload registers must first be cleared to all zeros. it should be noted that after power-on, the preload register will be in an unknown condition. note that if the timer/event counter is switched off and data is written to its preload registers, this data will be immediately written into the actual timer registers. however, if the timer/event counter is enabled and counting, any new data written into the preload data registers during this period will remain in the preload registers and will only be written into the timer registers the next time an overflow occurs. for the 16-bit timer/event counter which has both low byte and high byte timer registers, accessing these registers is carried out in a specific way. it must be noted when using instructions to preload data into the low byte timer register, the data will only be placed in a low byte buffer and not directly into the low byte timer register. the actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely tmr1h, is executed. on the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. at the same time the data in the low byte buffer will be transferred into its associated low byte timer register. for this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. it must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associated low byte buffer. after this has been done, the low byte timer register can be read in the normal way. note that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 51 december 2, 2011
timer control registers tmr0c, tmr1c, tmr2c, tmr3c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. it is the timer control register together with its corresponding timer registers that control the full operation of the timer/event counters. before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the corresponding timer control register, which are known as the bit pair tnm1/tnm0, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as tnon, depending upon which timer is used, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. for timers that have prescalers, bits 0~2 of the timer control register determine the division ratio of the input clock prescaler. the prescaler bit settings have no effect if an external clock source is used. if the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as tne. an additional tns bit in the 16-bit timer/event counter control register is used to determine the clock source for the timer/event counter. timer/event counter control register tmrnc (n=0, 2, 3) b i t76543210 name tnm1 tnm0 tnon tne tnpsc2 tnpsc1 tnpsc0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 01000 bit 7~6 tnm1~tnm0 : timer/event counter operating mode selection bit 00: no mode available 01: event counter mode 10: timer mode 11: pulse width measurement mode bit 5 unimplemented, read as 0 bit 4 tnon : timer/event counter counting enable control 0: disable 1: enable bit 3 tne : timer/event counter active edge selection bits for event counter mode: 0: count on rising edge 1: count on falling edge for pulse width measurement mode: 0: start counting on falling edge 1: start counting on rising edge bit 2~0 tnpsc2~tnpsc0 : timer/event counter prescaler rate selection bits 000: 1 / 1 001: 1 / 2 010: 1 / 4 011: 1 / 8 100: 1 / 16 101: 1 / 32 110: 1 / 64 111: 1 / 128 rev. 1.00 52 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
timer/event counter control register tmrnc (n=1) b i t76543210 name tnm1 tnm0 tns tnon tne r/w r/w r/w r/w r/w r/w p o r00001 bit 7~6 tnm1~tnm0 : timer/event counter operating mode selection bit 00: no mode available 01: event counter mode 10: timer mode 11: pulse width measurement mode bit 5 tns : timer/event counter clock source selection bit 0: f sys /4 1: f sub bit 4 tnon : timer/event counter counting enable control 0: disable 1: enable bit 3 tne : timer/event counter active edge selection bits for event counter mode: 0: count on rising edge 1: count on falling edge for pulse width measurement mode: 0: start counting on falling edge 1: start counting on rising edge bit 2~0 unimplemented, read as 0 configuring the timer mode in this mode, the timer/event counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the timer/event counter overflows. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 10 in this mode the internal clock, f sys , is used as the internal clock for 8-bit timer/event counters and f sub or f sys /4 is used as the internal clock for 16-bit timer/event counter. however, the clock source, f sys , for the 8-bit timer is further divided by a prescaler, the value of which is determined by the prescaler rate select bits tnpsc2~tnpsc0, which are bits 2~0 in the timer control register. after the other bits in the timer control register have been setup, the enable bit tnon or tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. each time an internal clock cycle occurs, the timer/event counter increments by one. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 53 december 2, 2011

b :
b +
b 6
b 6 b : timer mode timing chart
configuring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the timer/event counter. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 01 in this mode, the external timer pin, is used as the timer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, tne, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the active edge select bit is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero. as the external timer pin is shared with an i/o pin, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. configuring the pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width measurement mode bit7 bit6 11 in this mode the internal clock, f sys , is used as the internal clock for the 8-bit timer/event counter and f sub or f sys /4 is used as the internal clock for the 16-bit timer/event counter. however, the clock source, f sys , for the 8-bit timer is further divided by a prescaler, the value of which is determined by the prescaler rate select bits tnpsc2~tnpsc0, which are bits 2~0 in the timer control register. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit tne, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select rev. 1.00 54 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
b + ! " ! (

b *
b : event counter mode timing chart
bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width measurement mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. not until the enable bit is again set high by the program can the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero. as the external timer pin is shared with an i/o pin, to ensure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width measurement mode, the second is to ensure that the port control register configures the pin as an input. programmable frequency divider pfd the programmable frequency divider provides a means of producing a variable frequency output suitable for applications requiring a precise frequency generator. the pfd output is pin-shared with the i/o pin pa3. the pfd function is selected via configuration option, however, if not selected, the pin can operate as a normal i/o pin. the clock source for the pfd circuit can originate from either timer/event counter 0 or timer/event counter 1 overflow signal selected via configuration option. the output frequency is controlled by loading the required values into the timer registers and prescaler registers to give the required division ratio. the timer will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the pfd output to change state. the timer will then be automatically reloaded with the preload register value and continue counting-up. for the pfd output to function, it is essential that the corresponding bit of the port a control register pac bit 3 is setup as an output. if setup as an input the pfd output will not function, however, the pin can still be used as a normal input pin. the pfd output will only be activated if bit pa3 is set to 1 . this output data bit is used as the on/off control bit for the pfd output. note that the pfd output will be low if the pa3 output data bit is cleared to 0 . HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 55 december 2, 2011 b : b + b * b 7
! "
6 3
! k 9 /

( )
) : , pulse width measure mode timing chart
using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated. prescaler bits tnpsc0~tnpsc2 of the control register can be used to define the pre-scaling stages of the internal clock source of the timer/event counter. the timer/event counter overflow signal can be used to generate signals for the pfd and timer interrupt. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, require the use of external pins for correct operation. as these pins are shared pins they must be configured correctly to ensure they are setup for use as timer/event counter inputs and not as a normal i/o pins. this is implemented by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width measurement mode. additionally the port control register must be set high to ensure that the pin is setup as an input. any pull-high resistor on these pins will remain valid even if the pin is used as a timer/event counter input. timer/event counter pins internal filter the external timer/event counter pins are connected to an internal filter to reduce the possibility of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or spikes on the external timer/event counter input signal. as this internal filter circuit will consume a limited amount of power, several control bits named tmnflt in the rcflt register are provided to switch off the filter function, a choice which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high. rev. 1.00 56 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
( ) 3 5 ' / $ * ' 5 ' $ * pfd output control
rc filter control register rcflt bit76543210 name int1flt int0flt tm3flt tm2flt tm1flt tm0flt r/w r/w r/w r/w r/w r/w r/w por 001000 bit 7~6 unimplemented, read as 0 bit 5 int1flt : external interrupt 1 input rc filter enable control 0: disable 1: enable bit 4 int0flt : external interrupt 0 input rc filter enable control 0: disable 1: enable bit 3 tm3flt : timer/event counter 3 input rc filter enable control 0: disable 1: enable bit 2 tm2flt : timer/event counter 2 input rc filter enable control 0: disable 1: enable bit 1 tm1flt : timer/event counter 1 input rc filter enable control 0: disable 1: enable bit 0 tm0flt : timer/event counter 0 input rc filter enable control 0: disable 1: enable programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly initialised before using them for the first time. the associated timer interrupt enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 57 december 2, 2011
when the timer/event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the halt instruction to enter the power down mode. timer program example this program example shows how the timer/event counter registers are setup, along with how the interrupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; smart card interrupt vector reti org 08h ; usb interrupt vector reti org 0ch ; external interrupt 0 vector reti org 10h ; external interrupt 1 vector reti org 14h ; timer/event counter 0 interrupt vector jmp tmr0int ; jump here when the timer/event counter 0 overflows : org 2ch ;internal timer/event counter 0 interrupt routine tmr0int: : ; timer/event counter 0 main program placed here reti : : begin: ;setup timer 0 registers mov a,09bh ; setup timer 0 preload value mov tmr0,a; mov a,081h ; setup timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,002h ; timer 0 interrupt intc1,a set intc0.0 ; enable master interrupt set tmr0c.4 ; start timer/event counter 0 - note mode bits must be previously setup rev. 1.00 58 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
pulse width modulator the device contains a series of pulse width modulation, pwm, outputs. useful for the applications such as motor speed control, the pwm function provides an output with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm register. pwm mode channels output pin register names pwm0 8+4 pc4 pwm0h/pwm0l pwm1 8+4 pc5 pwm1h/pwm1l pwm2 8+4 pc6 pwm2h/pwm2l pwm3 8+4 pa5 pwm3h/pwm3l pwm overview a register pair, located in the data memory is assigned to each pulse width modulator output and are known as the pwm registers. it is in each register pair that the 12-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. the pwm registers also contain the enable/disable control bit for the pwm outputs. to increase the pwm modulation frequency, each modulation cycle is modulated into sixteen individual modulation sub-sections, known as the 8+4 mode. note that it is only necessary to write the required modulation value into the corresponding pwm register as the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 16 sub-cycles enables the generation of higher pwm frequencies, which allow a wider range of applications to be served. as long as the periods of the generated pwm pulses are less than the time constants of the load, the pwm output will be suitable as such long time constant loads will average out the pulses of the pwm output. the difference between what is known as the pwm cycle frequency and the pwm modulation frequency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 12-bits wide, the overall pwm cycle frequency is f sys /4096. however, when in the 8+4 mode of operation, the pwm modulation frequency will be f sys /256. pwm modulation frequency pwm cycle frequency pwm cycle duty f sys /256 f sys /4096 (pwm register value)/4096 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 59 december 2, 2011
8+4 pwm mode modulation each full pwm cycle, as it is 12-bits wide, has 4096 clock periods. however, in the 8+4 pwm mode, each pwm cycle is subdivided into sixteen individual sub-cycles known as modulation cycle 0 ~ modulation cycle 15, denoted as i in the table. each one of these sixteen sub-cycles contains 256 clock cycles. in this mode, a modulation frequency increase of sixteen is achieved. the 12-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the first group which consists of bit4~bit11 is denoted here as the dc value. the second group which consists of bit0~bit3 is known as the ac value. in the 8+4 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac (0~15) dc (duty cycle) modulation cycle i (i=0~15) i ac dc+1 256 iac dc 256 8+4 mode modulation cycle values the accompanying diagram illustrates the waveforms associated with the 8+4 mode of pwm opera - tion. it is important to note how the single pwm cycle is subdivided into 16 individual modulation cycles, numbered 0~15 and how the ac value is related to the pwm value. pwm output control the four pwm0~pwm3 outputs are shared with i/o pins. to operate as a pwm output and not as an i/o pin, the relevant pwm enable control bit in pwmnl register must be set high where n denotes 0 from 3. a zero must also be written to the corresponding bit in the relevant port control register, to ensure that the pwm output pin is setup as an output. after these two initial steps have been carried out, and of course after the required pwm 12-bit value has been written into the pwm register pair register, writing a 1 to the corresponding port data register will enable the pwm data to appear on the pin. writing a 0 to the bit will disable the pwm output function and force the output low. in this way, the port data register bits, can also be used as an on/off control for the pwm function. note that if the enable bit in the pwmnl register is set high to enable the pwm function, but a 1 has been written to its corresponding bit in the port control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor selections. rev. 1.00 60 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces ) c & + f g k : . 9 9 f g k : . 9 : f g k : . 9 + f g k : . : 8 d 7 9 = . & ) c : 9 9 & + 8 . : 9 : & + 8 . : 9 : & + 8 . : 9 : & + 8 .
9

d + 8 . & ) c
:
+
: 8
9 : 9 9 & + 8 . : 9 9 & + 8 . : 9 9 & + 8 . : 9 : & + 8 . : 9 9 & + 8 . : 9 : & + 8 . : 9 : & + 8 . : 9 : & + 8 . : 9 9 & + 8 . : 9 9 & + 8 . : 9 9 & + 8 . : 9 9 & + 8 . : 9 9 & + 8 . : 9 : & + 8 . : 9 : & + 8 . : 9 : & + 8 . 8+4 pwm mode
pwm register pairs pwmnh/pwmnl (n=0~3) pwmnh register bit76543210 name d11 d10 d9 d8 d7 d6 d5 d4 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 pwmnl register bit76543210 name d3 d2 d1 d0 pwmnen r/w r/w r/w r/w r/w r/w por0000 0 unimplemented, read as 0 d11~d4 : pwmn duty dc value d3~d0 : pwmn duty ac value pwmnen : pwmn output enable control 0: i/o pin enable 1: pwm output pin enable pwm programming example the following sample program shows how the pwm output is setup and controlled. mov a,64h ; setup pwm0 value to 1600 decimal which is 640h mov pwm0h,a ; setup pwm0h register value clr pwm0l ; setup pwm0l register value clr pcc.4 ; setup pin pc4 as an output set pwm0en ; set the pwm0 enable bit set pc.4 ; enable the pwm0 output :: :: clr pc.4 ; pwm0 output disabled - pc4 will remain low HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 61 december 2, 2011
analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. a/d overview the device contains an 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. input channels conversion bits input pins 8 12 pa0~pa7 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. a/d converter data registers adrl, adrh the device, which has an internal 12-bit a/d converter, requires two data registers, a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. only the high byte register, adrh, utilises its full 8-bit contents. the low byte register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. in the following table, d0~d11 is the a/d conversion data result bits. register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adrl d3 d2 d1 d0 adrh d11 d10 d9 d8 d7 d6 d5 d4 a/d data registers rev. 1.00 62 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces $ & ' ( $ 9 & $ 6 9 $ : & $ 6 : $ - & $ 6 - $ & ' ) 4 $ ' % $ ' 0 $ & ' '
4 2 < ! 6 $ ! 2 $ ' 6 2 4 $ - & $ 6 - & 4 ! 5 $ ' + h $ ' 9 ) c - h 9 $ 7 e $ + h $ 9 : , + 8 4 $ & ' / 4 ' ' $ ' 6 2 2
4 ! 5 2
+ 6 @ 6 k 9 h 8 a a/d converter structure
a/d converter control registers adcr, adpcr, acsr to control the function and operation of the a/d converter, three control registers known as adcr, adpcr and acsr are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, which pins are used as analog inputs and which are used as normal i/os, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs4, acs2~acs0 bits in the register and the acs4 bit in the acsr register define the channel number. as the device contains only one actual analog to digital converter circuit, each of the individual 8 analog inputs must be routed to the converter. it is the function of the acs2~acs0 bits in the adcr register and the acs4 bit in the acsr register to determine which analog channel is actually connected to the internal a/d converter. the adpcr control register contains the pcr7~pcr0 bits which determine which pins on port a are used as analog inputs for the a/d converter and which pins are to be used as normal i/o pins. if the pcrn bit has a value of 1, the related pin on port a will be set as an analog input. if the pcrn bit is set to zero, then the related pin on port a will be setup as a normal i/o pin. acsr register b i t76543210 name test adonb acs4 vbgen vrefs adcs2 adcs1 adcs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por11000000 bit 7 test : for test only, read as 1 bit 6 adonb : a/d converter enable control 0: a/d converter is turned on 1: a/d converter is turned off bit 5 acs4 : internal band-gap reference voltage channel input selection 0: a/d converter analog channel is connected to the analog input from an0 to an/7 1: a/d converter analog channel is connected to the internal band-gap voltage vbg bit 4 vbgen : band-gap reference voltage enable control 0: band-gap voltage v bg is disabled and connected to the ground 1: band-gap voltage v bg is enabled the band-gap reference voltage v bg is used for the a/d converter and lvd/lvr function, which is controlled by the band-gap reference voltage enable bit vbgen in the acsr register. if the vbg is not used for the a/d converter and the lvd/lvr function is disabled, the microcontroller hardware will automatically turned off the band-gap reference voltage to conserve power. care must be taken as when the vrefs bit is set high for the a/d converter, then a v bg turn on time t bg must be allowed before any a/d conversions are implemented. bit 3 vrefs : a/d converter reference voltage selection bit 0: from the internal voltage av dd 1: from the external pin vref the a/d reference voltage can come from either the internal voltage avdd or the external voltage v ref , which is selected by the vrefs bit in the acsr register. when the vrefs bit is cleared to 0, the reference voltage of the a/d converter comes from the internal a/d power supply vadd and the external vref pin can be used as an i/o pin or other pin-shared function. when the vrefs bit is set to 1, the reference voltage of the a/d converter comes from the external vref pin and the i/o or other pin-shared functions are disabled. bit 2~0 adcs2~adcs0 : select a/d converter clock source 000: f sys /2 001: f sys /8 010: f sys /32 011: undefined 100: f sys 101: f sys /4 110: f sys /16 111: undefined HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 63 december 2, 2011
adcr register b i t76543210 name start eocb acs2 acs1 acs0 r/w r/w r r/w r/w r/w por 0 1 000 bit 7 start : start the a/d conversion 01 0 : start 0 1 : reset the a/d converter and set eocb to 1 bit 6 eocb : end of a/d conversion flag 0: a/d conversion ended 1: a/d conversion waiting or in progress bit 5~3 unimplemented, read as 0 bit 2~0 acs2~acs0 : a/d converter channel selection bits 000: an0 is selected 001: an1 is selected 010: an2 is selected 011: an3 is selected 100: an4 is selected 101: an5 is selected 110: an6 is selected 111: an7 is selected only valid if acs4=0 adpcr register b i t76543210 name pcr7 pcr6 pcr5 pcr4 pcr3 pcr2 pcr1 pcr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 pcr7~pcr0 : a/d converter analog channel configuration 0: i/o pin or other pin-shared function 1: a/d analog channel when the related bit is set to 1, the corresponding pin is used as an analog input and all other pin-shared functions are disabled automatically. the start bit in the register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initi - ated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr register will be set to a 1 and the analog to digital converter will be reset. it is the start bit that is used to control the overall on/off operation of the internal analog to digital converter. the eocb bit in the adcr register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , is first divided by a division ratio, the value of which is determined by the adcs2, adcs1 and adcs0 bits in the acsr register. rev. 1.00 64 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
controlling the on/off function of the a/d converter circuitry is implemented using the adonb bit in the acsr register. when the adonb bit is cleared to 0, the a/d converter is enabled. although the a/d clock source is determined by the system clock f sys , and by bits adcs2~adcs0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t ad ,is0.5 s, care must be taken for system clock frequencies equal to or greater than 4mhz. for example, if the system clock operates at a frequency of 4mhz, the adcs2~adcs0 bits should not be set to 100 . doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum a/d clock period. f sys a/d clock period (t ad ) adcs=000 (t ad =2/f sys ) adcs=001 (t ad =8/f sys ) adcs=010 (t ad =32/f sys ) adcs=011 (undefined) adcs=100 (t ad =1/f sys ) adcs=101 (t ad =4/f sys ) adcs=110 (t ad =16/f sys ) adcs=111 (undefined) 1mhz 2 s8 s3 2 s undefined 1s4 s1 6 s undefined 2mhz 1 s4 s1 6 s undefined 500ns 2s8 s undefined 4mhz 500ns 2s8 s undefined 250ns* 1s4 s undefined 8mhz 250ns* 1s s undefined 125ns* 500ns 2 s undefined 12mhz 167ns* 667ns 2.67 s undefined 83ns* 333ns* 1.33 s undefined a/d clock period examples a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a. bits pcr7~pcr0 in the adpcr register, determine whether the input pins are setup as normal input/output pins or whether they are setup as analog inputs. in this way, pins can be changed under program control to change their function from normal i/o operation to analog inputs and vice versa. pull-high resistors, which are setup through register programming, apply to the input pins only when they are used as normal i/o pins, if setup as a/d inputs the pull-high resistors will be automatically disconnected. note that it is not necessary to first setup the a/d pin as an input in the port control register to enable the a/d input as when the pcr7~pcr0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own power supply pins avdd and avss and a vref reference pin. the analog input values must not be allowed to exceed the value of vref. initialising the a/d converter the internal a/d converter must be initialised in a special way. each time the a/d channel selection bits are modified by the program, the a/d converter must be re-initialised. if the a/d converter is not initialised after the channel selection bits are changed, the eocb flag may have an undefined value, which may produce a false end of conversion signal. to initialise the a/d converter after the channel selection bits have changed, then the start bit in the adcr register must first be set high and then immediately cleared to zero. this will ensure that the eocb flag is correctly set to a high condition. summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. step 1 select the required a/d conversion clock by correctly programming bits adcs2, adcs1 and adcs0 in the register. step 2 enable the a/d by clearing the in the acsr register to zero. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 65 december 2, 2011
step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4, acs2~acs0 bits which are also contained in the register. step 4 select which pins on the i/o port are to be used as a/d inputs and configure them as a/d input pins by correctly programming the pcr7~pcr0 bits in the adpcr register. step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, in the intc0 interrupt control register must be set to 1 and the a/d converter interrupt enable bit, eadi, in the intc2 register must also be set to 1 . step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr register from 0 to 1 and then to 0 again. note that this bit should have been originally set to 0 . step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note when checking for the end of the conversion process, if the method of polling the bit in the adcr register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. the setting up and operation of the a/d converter function is fully under the control of the application program as there are no configuration options associated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t ad where t ad is equal to the a/d clock period. rev. 1.00 66 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces $ ' $ & ' (

9 9 9 9 9 9 9 9 2 " " " 2 9 9 9 9 9 : 9 9 2 9 : 9 2 $ ! 2 - h 9 $ + h $ 9 l 3 ! ) $ & ' (
: d ' )
)

+ d $ & ' / ) c e ) c & + e ) c & 7 e ) c & e ) c & : . ) c & * + $ ' k 7 $ ' $ ' k $ ' b l $ ' > k
) $ '
i l i (

) $ 7 k 9 6 d ) $ & ' (
$ & ' ( $ & '

$ ' 9 9 9 2 ) $ & ' (
$ & ' ( 9 9 9 9 9 : 9 : 2 9 9 : 2 ) $ & ' (
$ & ' ( ! ) $ & ' (
$ & '

$ ' 9 9 9 9 9 9 9 9 2 " " " 2 $ ' 6 $ ' 6 2 ) ) ) ) 6 + $ ' $ & ' (

a/d conversion timing
programming considerations the a/d converter can be powered down by setting the adonb bit in acsr register to reduce power consumption. it is an important ability for some applications such as battery powered or handheld appliance. another important programming consideration is that when the a/d channel selection bits change value, the a/d converter must be re-initialised. this is achieved by pulsing the start bit in the adcr register immediately after the channel selection bits have changed state. the exception to this is where the channel selection bits are all cleared, in which case the a/d converter is not required to be re-initialised. a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the first example, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; select f sys /8 as a/d clock and turn on adonb bit mov a,0fh ; setup adpcr register to configure port a pin pa0~pa3 mov adpcr,a, ; as a/d inputs mov a,00h ; and select an0 to be connected to the a/d converter mov adcr,a : : ; as the port a channel bits have changed the ; following start ; signal (0-1-0) must be issued ; instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_: sz eocb ; poll the adcr register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : jmp start_conversion ; start next a/d conversion HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 67 december 2, 2011
example: using the interrupt method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; select f sys /8 as a/d clock and turn on adonb bit mov a, 0fh mov adpcr,a ; setup adpcr register to configure port a pin pa0~pa3 mov a, 00h ; as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : ; as the port a channel bits have changed the ; following start signal(0-1-0) must be issued ; : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set eadi ; enable adc interrupt set emi ; enable global interrupt : : : ; adc interrupt service routine adc_: mov acc_stack,a ; save acc to user defined memory mov a,status mov status_stack,a ; save status to user defined memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : exit__isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory clr adf ; clear adc interrupt flag reti rev. 1.00 68 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
a/d transfer function as the device contains a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of (v dd or v ref /4096). the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. note that to reduce the quantisation error, a 0.5 lsb offset is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitized value will change at a point 1.5 lsb below the v dd or v ref level. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 69 december 2, 2011 5 5 ! 0 @ a $ & ' (
5 5 5 0 5 5 ' 0 9 * 0 9 + 0 9 : 0 9 , 8 % 2 9 : + * 7 9 = * 7 9 = 7 7 9 = 8 7 9 = . $ 4 : , 8 % 2 4 ' ' 4 ! 5 7 9 = . ideal a/d transfer function
serial interface function sim the device contains two serial interface modules named sim0 and sim1 to implement serial interface function, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim interface function must first be selected using a configuration option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using a bit in an internal register. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the mcu can be either master or slave. although the spi interface specification can control multiple slave devices from a single master, here, as only a single select pin, scs , is provided only one slave device can be connected to the spi bus. rev. 1.00 70 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces ' ( % ' ( ' ) * ; ' ' ; ' ' spi master/slave connection ' 2 '
'
' " & "
)
2 )

5 5 ! & '
% 5 / ! &
/ ) c ) 2
& ! ( ;

)

! 6
! & '
; ! <
; %
spi block diagram
spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdin, sdon, sckn and scsn where n stands for 0 and 1 respectively. pins sdin and sdon are the serial data input and serial data output lines, sckn is the serial clock line and scsn is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i2c function pins, the spi interface must first be enabled by selecting the simn enable configuration options and setting the correct bits in the simnctl0/simnctl2 register. after the simn configuration option has been configured it can also be additionally disabled or enabled using the simnen bit in the simnctl0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as each sim only contains a single scs pin, only one slave device can be utilized for each sim. the spi function in this device offers the following features: full duplex synchronous data transfer both master and slave modes lsb first or msb first data transmission modes transmission complete flag rising or falling active clock edge wcoln and csenn bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csenn, simnen and scsn . in the table i, z represents an input floating condition. there are several configuration options associated with the spi interface. one of these is to enable the simn function which selects the simn pins rather than normal i/o pins. note that if the configuration option does not select the simn function then the simnen bit in the simnctl0 register will have no effect. another two simn configuration options determine if the csenn and wcoln bits are to be used. configuration option function simn function simn interface or i/o pins spi csenn bit enable/disable spi wcoln bit enable/disable spi interface configuration options HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 71 december 2, 2011
sim0 control register 0 sim0ctl0 b i t76543210 name s0sim2 s0sim1 s0sim0 pcken pckpsc1 pckpsc0 sim0en r/w r/w r/w r/w r/w r/w r/w r/w p o r1110000 bit 7~5 s0sim2~s0sim0 : sim0 mode and clock selection 000: sim0 in spi master mode with f sys /4 clock source 001: sim0 in spi master mode with f sys /16 clock source 010: sim0 in spi master mode with f sys /64 clock source 011: sim0 in spi master mode with f sub clock source 100: sim0 in spi master mode with timer/event counter 0 overflow/2 clock (pfd0) 101: sim0 in spi slave mode 110: sim0 in i 2 c mode 111: reserved bit 4 pcken : peripheral clock pck enable control 0: pck output is disabled 1: pck output is enabled bit 3~2 pckpsc1~pckpsc0 : peripheral clock pck output clock prescaler 00: f sys 01: f sys /4 10: f sys /8 11: timer/event counter 0 overflow /2 (pfd0) bit 1 sim0en : sim0 enable control 0: sim0 is disabled 1: sim0 is enabled bit 0 unimplemented, read as 0 sim1 control register 0 sim1ctl0 bit76543210 name s1sim2 s1sim1 s1sim0 sim1en r/w r/w r/w r/w r/w por 1 1 1 0 bit 7~5 s1sim2~s1sim0 : sim1 mode and clock selection 000: sim1 in spi master mode with f sys /4 clock source 001: sim1 in spi master mode with f sys /16 clock source 010: sim1 in spi master mode with f sys /64 clock source 011: sim1 in spi master mode with f sub clock source 100: sim1 in spi master mode with timer/event counter 0 overflow/2 clock (pfd0) 101: sim1 in spi slave mode 110: sim1 in i 2 c mode 111: reserved bit 4~2 unimplemented, read as 0 bit 1 sim1en : sim1 enable control 0: sim1 is disabled 1: sim1 is enabled bit 0 unimplemented, read as 0 rev. 1.00 72 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
simn control register 1 simnctl1 (n=0 or 1) for i 2 c mode b i t76543210 name hcfn haasn hbbn htxn txakn srwn rxakn r/w r/w r/w r/w r/w r/w r/w r/w p o r100000 0 bit 7 hcfn:i 2 c bus data transfer completion flag 0: data is being transferred 1: completion of an 8-bit data transfer the hcfn flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haasn:i 2 c bus address match flag 0: no address match 1: address match the haasn flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the addresses match, then this bit will be high. if there is no address match, then the flag will be low. bit 5 hbbn:i 2 c bus busy flag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbbn flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htxn : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txakn:i 2 c bus transmit acknowledge flag 0: slave sends acknowledge flag 1: slave does not send acknowledge flag the txakn bit is the transmit acknowledge flag. after the slave device receipt of 8-bit of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txakn bit to 0 before further data is received. bit 2 srwn :i 2 c slave read/write flag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srwn flag is the i 2 c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data to or from the i 2 c bus. when the transmitted address and slave address is match, that is when the haasn flag is set high, the slave device will check the srwn flag to determine whether it should be in transmit mode or receive mode. if the srwn flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srwn flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 unimplemented, read as 0 bit 0 rxakn:i 2 c bus receive acknowledge flag 0: slave receives acknowledge flag 1: slave does not receive acknowledge flag the rxakn flag is the receiver acknowledge flag. when the rxakn flag is 0, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxakn flag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxakn flag is 1. when this occurs, the slave transmitter will release the sdan line to allow the master to send a stop signal to release the i 2 c bus. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 73 december 2, 2011
simn control register 2 simnctl2 (n=0 or 1) for spi mode b i t76543210 name ckpoln ckegn mlsn csenn wcoln trfn r/w r/w r/w r/w r/w r/w r/w por 000000 bit 7~6 undefined bit, read as 0 bit 5 ckpoln : determines the base condition of the spi clock line 0: the sckn line will be high when the spi clock is inactive 1: the sckn line will be low when the spi clock is inactive the ckpoln bit determines the base condition of the spi clock line, if the bit is high, then the sckn line will be low when the clock is inactive. when the ckpoln bit is low, then the sckn line will be high when the clock is inactive. bit 4 ckegn : determines spi sckn active clock edge type ckpoln=0 0: sckn is high base level and data capture at sckn rising edge 1: sckn is high base level and data capture at sckn falling edge ckpoln=1 0: sckn is low base level and data capture at sckn falling edge 1: sckn is low base level and data capture at sckn rising edge the ckegn and ckpoln bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpoln bit determines the base condition of the clock line. if the bit is high, then the sckn line will be low when the clock is inactive. when the ckpoln bit is low, then the sckn line will be high when the clock is inactive. the ckegn bit determines active clock edge type which depends upon the condition of ckpoln bit. bit 3 mlsn : spi data shift order 0: lsb shift first 1: msb shift first this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. bit 2 csenn : spi scsn pin control 0: disable 1: enable the csenn bit is used as an enable/disable for the scsn pin. if this bit is low, then the scsn pin will be disabled and placed into a floating condition. if the bit is high the scsn pin will be enabled and used as a select pin. note that using the csenn bit can be disabled or enabled via configuration option. bit 1 wcoln : spi write collision flag 0: no collision 1: collision the wcoln flag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simndr register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcoln bit can be disabled or enabled via configuration option. bit 0 trfn : spi transmit/receive complete flag 0: data is being transferred 1: spi data transmission is completed the trfn bit is the transmit/receive complete flag and is set to 1 automatically when an spi data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt. rev. 1.00 74 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
spi registers there are three internal registers which control the overall operation of the spi interface for each sim. these are the simndr data register and two control registers simnctl0 and simnctl2. note that the simnctl1 register is only used by the i 2 c interface. pin master/salve simnen=0 master simnen=1 slave simnen=1 csenn=1 csenn=0 csenn=0 scsn line=0 (csenn=1) scsn line=1 (csenn=1) scsn zl z zi , zi , z sdon z ooooz sdin z i, z i, z i, z i, z z sckn z h: ckpoln=0 l: ckpoln=1 h: ckpoln=0 l: ckpoln=1 i, z i, z z note: z floating, h output high, l output low, i input, o output level, i,z input floating (no pull-high) spi interface pin status the simndr register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the microcontroller writes data to the spi bus, the actual data to be transmitted must be placed in the simndr register. after the data is received from the spi bus, the microcontroller can read it from the simndr register. any transmission or reception of data from the spi bus must be made via the simndr register. b i t76543210 label snd7 snd6 snd5 snd4 snd3 snd2 snd1 snd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por xxxxxxxx there are also two control registers for the spi interface, simnctl0 and simnctl2. note that the simnctl2 register also has the name simnar which is used by the i 2 c function. the simnctl1 register is not used by the spi function, only by the i 2 c function. register simnctl0 is used to con- trol the enable/disable function and to set the data transmission clock frequency. although not con- nected with the spi function, the simnctl0 register is also used to control the peripheral clock prescaler. register simnctl2 is used for other control functions such as lsb/msb selection, write collision flag etc. the following gives further explanation of each sim related register bit. simidle the simidle bit is used to select if the master spi interface continues running when the device is in the idle mode. setting the bit high allows the clock source of the master spi interface or the peripheral clock pclk, which is selected to come from the divided system clock, to keep active when the device is in the idle mode. this will maintain the master spi interface operation or the peripheral clock pclk output active if the pcken bit is set to 1 in idle mode. clearing the bit to zero disables any master spi interface operations or pclk output in the idle mode. this spi/i 2 c idle mode control bit simidle is located at clkmod register bit4. simnen the bit is the overall on/off control for the spi interface. when the simnen bit is cleared to zero to disable the spi interface, the sdin, sdon, sckn and scsn lines will be in a floating condition and the spi operating current will be reduced to a minimum value. when the bit is high the spi interface is enabled. the simn configuration option must have first enabled the simn interface for this bit to be effective. note that when the simnen bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be first initialised by the application program. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 75 december 2, 2011
rev. 1.00 76 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces ; @ ; % k : a ; @ ; % k 9 a ' ' ' ' - & ' 9 ' . & ' : ' 8 & ' + ' 7 & ' * ' * & ' 7 ' + & ' 8 ' : & ' . ' 9 & ' -
' @ '
)
; a spi slave mode timing (ckegn=0) ; @ ; % k : e ; ! < k 9 a ! 6 e ! 6 k : ! 6 k : e ! 6 k 9 @ ! " 0
a ; @ ; % k 9 e ; ! < k 9 a ; @ ; % k : e ; ! < k : a ; @ ; % k 9 e ; ! < k : a ' @ ; ! < k 9 a ' @ ; ! < k : a ' ' ' - & ' 9 ' . & ' : ' 8 & ' + ' 7 & ' * ' * & ' 7 ' + & ' 8 ' : & ' . ' 9 & ' - ' - & ' 9 ' . & ' : ' 8 & ' + ' 7 & ' * ' * & ' 7 ' + & ' 8 ' : & ' . ' 9 & ' -
' spi master mode timing ; @ ; % k : a ; @ ; % k 9 a ' ' ' ' - & ' 9 ' . & ' : ' 8 & ' + ' 7 & ' * ' * & ' 7 ' + & ' 8 ' : & ' . ' 9 & ' -
' @ ' 3

> ' k )

) k : a 6 d 5 ( e
) ! 6 k : ! 6 k 9 e
3
( , spi slave mode timing (ckegn=1)
simn0~simn2 these bits setup the overall operating mode of the simn function. as well as selecting if the i 2 cor spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the timer/event counter 0. if the spi slave mode is selected then the clock will be supplied by an external master device. simn_0 simn_1 simn_2 spi master/slave clock control and i 2 c enable 0 0 0 spi master, f sys /4 0 0 1 spi master, f sys /16 0 1 0 spi master, f sys /64 0 1 1 spi master, f sub 1 0 0 spi master timer/event counter 0 overflow/2 1 0 1 spi slave 110i 2 c mode 1 1 1 not used HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 77 december 2, 2011 ! 6 k :
'
' % k : m % c

m @ 5 k : m a 6 c ' ) ' 5 ) 5

m 6 c ! 6 ' ( ( $ $ ) )
! 6 % f + d 9 g k 9 9 9 e 9 9 : e 9 : 9 e 9 : : : 9 9 f + d 9 g k : 9 : 6 spi transfer control flowchart
spi control register simnctl2 the simnctl2 register is also used by the i 2 c interface but has the name simnar. trfn the trfn bit is the transmit/receive complete flag and is set high automatically when an spi data transmission is completed, but must be cleared by the application program. it can be used to generate an interrupt. wcoln the wcoln bit is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simndr register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcoln bit can be disabled or enabled via configuration option. csenn the csenn bit is used as an on/off control for the scsn pin. if this bit is low then the scsn pin will be disabled and placed into a floating condition. if the bit is high the scsnb pin will be enabled and used as a select pin. note that using the csenn bit can be disabled or enabled via configuration option. mls this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. ckegn and ckpoln these two bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpoln bit determines the base condition of the clock line, if the bit is high then the sckn line will be low when the clock is inactive. when the ckpoln bit is low then the sckn line will be high when the clock is inactive. the ckegn bit determines active clock edge type which depends upon the condition of ckpoln. ckpoln ckegn sckn clock signal 0 0 high base level active rising edge 0 1 high base level active falling edge 1 0 low base level active falling edge 1 1 low base level active rising edge rev. 1.00 78 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
spi communication after the spi interface is enabled by setting the simnen bit high, then in the master mode, when data is written to the simndr register, transmission/reception will begin simultaneously. when the data transfer is complete, the trfn flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simndr register will be transmitted and any data on the sdin pin will be shifted into the simndr register. the master should output a scsn signal to enable the slave device before a clock signal is provided and slave data transfers should be enabled/disabled before/after an scsn signal is received. the spi will continue to function even after a halt instruction has been executed. i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, , and serial clock line, scln. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identified by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several configuration options associated with the i 2 c interface. one of these is to enable the function which selects the simn pins rather than normal i/o pins. note that if the configuration option does not select the simn function then the simnen bit in the simnctl0 register will have no effect. a configuration option exists to allow a clock other than the system clock to drive the i 2 c interface. another configuration option determines the debounce time of the i 2 c interface. this uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks. configuration option function simn function simn interface or i/o pins i 2 c debounce no debounce, 1 system clock; 2 system clocks i 2 c interface configuration options HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 79 december 2, 2011
i 2 c registers there are three control registers associated with the i 2 c bus, simnctl0, simnctl1 and simnar and one data register, simndr. the simndr register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simndr register. after the data is received from the i 2 c bus, the microcontroller can read it from the simndr register. any transmission or reception of data from the i 2 c bus must be made via the simndr register. note that the simnar register also has the name simnctl2 which is used by the spi function. bits simidle, simnen and bits snsim2~snsim0 in registers simnctl0 and clkmod are used by the i 2 c interface. the simnctl0 register is shown in the above spi section. simidle when the device is in the idle mode, the simidle bit has no effect if the i 2 c interface is selected to be used. setting the bit high only allows the clock source of the peripheral clock pclk, which is selected to come from the divided system clock, to keep active when the device is in the idle mode. it will maintain the peripheral clock pclk output active if the pcken bit is set to 1 in idle mode. clearing the bit to zero disables the pclk output when the device is in the idle mode. this spi/i 2 c idle mode control bit simidle is located at clkmod register bit4. simnen the simnen bit is the overall on/off control for the i 2 c interface. when the simnen bit is cleared to zero to disable the i 2 c interface, the sdan and scln lines will be in a floating condition and the i 2 c operating current will be reduced to a minimum value. in this condition the pins can be used as normal i/o functions. when the bit is high the i 2 c interface is enabled. the simn configuration option must have first enabled the simn interface for this bit to be effective. note that when the simnen bit changes from low to high the contents of the i 2 c control registers will be in an unknown condition and should therefore be first initialised by the application program. simn_0~simn_2 these bits setup the overall operating mode of the simn function. to select the i 2 c function, bits simn_2~simn_0 should be set to the value 110. rev. 1.00 80 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces + '
@ ' a ( $
@ $ a
)
'

# $ 0 $ $ 2
+ '
% 2 ' 2
&
(

' ' ' 2 $ ! & '
$ / 3 & 3
( 2
0 2 2 2
0 # 2
%
' $
0 5 2
i 2 c block diagram
rxakn the rxakn flag is the reception acknowledge flag. when the rxakn bit has been reset to zero, it means that a correct acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when in the transmit mode, the transmitter checks the rxakn bit to determine if the receiver wishes to receive the next byte. the transmitter will therefore continue sending out data until the rxakn bit is set high. when this occurs, the transmitter will release the sdan line to allow the master to send a stop signal to release the bus. srwn the srwn bit is the slave read/write bit. this bit determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address match, which is when the haasn bit is set high, the device will check the srwn bit to determine whether it should be in transmit mode or receive mode. if the srwn bit is high, the master is requesting to read data from the bus, so the device should be in transmit mode. when the srwn bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. txakn the txakn flag is the transmission acknowledge flag. after the receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock. to continue receiving more data, this bit has to be reset to zero before further data is received. htxn the htxn flag is the transmit/receive mode bit. this flag should be set high to set the transmit mode and low for the receive mode. hbbn the hbbn flag is the i 2 c busy flag. this flag will be high when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be reset to zero when the bus is free which will occur when a stop signal is detected. haasn the haasn flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the flag will be low. hcfn the hcfn flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. i 2 c address register simnar the simnar register is also used by the spi interface but has the name simnctl2. the simnar register is the location where the 7-bit slave address of the microcontroller is stored. bits 1~7 of the simnar register define the microcontroller slave address. bit 0 is not defined. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the simnar register, the microcontroller slave device will be selected. note that the simnar register is the same register as simnctl2 which is used by the spi interface. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 81 december 2, 2011
i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. the first seven bits of the data will be the slave address with the first bit being the msb. if the address of the microcontroller matches that of the transmitted address, the haasn bit in the simnctl1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the microcontroller slave device must first check the condition of the haasn bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srwn bit. this bit will be checked by the microcontroller to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus. the following are steps to achieve this: step 1 write the slave address of the microcontroller to the i 2 c bus address register simnar. step 2 set the simnen bit in the simnctl0 register to 1 to enable the i 2 c bus. step 3 set the esimn bit of the interrupt control register to enable the i 2 c bus interrupt. rev. 1.00 82 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
( $ $ ! f + d 9 g k : : 9 ! ! 6 + 2 k m ! '
! !
) <
% ! 5
3 + 2 <
i 2 c bus initialisation flow chart
HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 83 december 2, 2011 ' : 9 : 9 9 : 99 : 9 9 : 9 : 9 : : k @ :
a $ k ( $ @ -
a k
@ :
a k ( (
/ 3
@ :
a ' k ' @
a $ k $ ; @ # $ ;
)
e # $ ;
)
( :
a k @ :
a % ' $ $ ; $ ; % ' $ ( $ $ ' $ ' $ $ ' $ ' $ i 2 c communication timing diagram 0 $ $ k : m 0 # k : m k : m c 6 c 6 # $ ; k : m c 6 6 ) ' ! c ' ) ' ! !
' ! 0 #
' ' 5 ' % 0 # % # $ ; ! ! % 0 # % # $ ; i 2 c bus isr flow chart
start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the microcontroller, which is only a slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbbn bit will be set. a start condition occurs when a high to low transition on the sdan line takes place when the scln line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the srwn bit of the simnctl1 register. the device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the microcontroller slave device will also set the status flag haasn when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haasn bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simndr register, or in the receive mode where it must implement a dummy read from the simndr register to release the scln line. simnar register b i t76543210 name sna6 sna5 sna4 sna3 sna2 sna1 sna0 r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxx x means unknown. bit 7~1 sna6~sna0:i 2 c slave address sna6~sna0 is the i 2 c slave address bit6~bit0. the simnar register is also used by the spi interface but has the name simnctl2. the simnar register is the location where the 7-bit slave address of the slave device is stored. bit7~bit1 of the simnar register define the device slave address. bit 0 is not defined. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the simnar register, the slave device will be selected. note that the simnar register is the same register address as simnctl2 which is used by the spi interface. bit 0 unimplemented bit. this bit can be read or written by user software program. rev. 1.00 84 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
srw bit the srwn bit in the simnctl1 register defines whether the microcontroller slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. if the srwn bit is set to 1 then this indicates that the master wishes to read data from the i 2 c bus, therefore the microcontroller slave device must be setup to send data to the i 2 c bus as a transmitter. if the srwn bit is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the microcontroller slave device must be setup to read data from the i 2 c bus as a receiver. acknowledge bit after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. this acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haasn bit is high, the addresses have matched and the microcontroller slave device must check the srwn bit to determine if it is to be a transmitter or a receiver. if the srwn bit is high, the microcontroller slave device should be setup to be a transmitter so the htxn bit in the simnctl1 register should be set to 1 if the srwn bit is low then the microcontroller slave device should be setup as a receiver and the htxn bit in the simnctl1 register should be set to 0 . data byte the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0 , before it can receive the next data byte. if the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the sdan line and the master will send out a stop signal to release control of the i 2 c bus. the corresponding data will be stored in the simndr register. if setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the simndr register. if setup as a receiver, the microcontroller slave device must read the transmitted data from the simndr register. receive acknowledge bit when the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as txakn, on the 9th clock. the microcontroller slave device, which is setup as a transmitter will check the rxakn bit in the simnctl1 register to determine if it is to send another data byte, if not then it will release the sdan line and await the receipt of a stop signal from the master. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 85 december 2, 2011 % ' $
' ' 3
data timing diagram
peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pclk, is shared with an i/o line, the required pin function is chosen via pcken in the sim0ctl0 register. the peripheral clock function is controlled using the sim0ctl0 register. the clock source for the peripheral clock output can originate from either the timer/event counter 0 overflow signal divided by two or a divided ratio of the internal fsys clock. the pcken bit in the sim0ctl0 register is the overall on/off control, setting the bit high enables the peripheral clock, clearing it disables it. the required division ratio of the system clock is selected using the pckpsc0 and pckpsc1 bits in the same register. if the system enters the sleep mode, the peripheral clock output will be disabled. rev. 1.00 86 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces ) c
& ! ( 9 ( ) 3
+ % ; & % ; & : e 7 e ; ! 6 ; 9 ; : peripheral clock block diagram
buzzer operating in a similar way to the programmable frequency divider, the buzzer function provides a means of producing a variable frequency output, suitable for applications such as piezo-buzzer driving or other external circuits that require a precise frequency generator. the bz and bz pins form a complementary pair, and are pin-shared with i/o pins, pa0 and pa1. a configuration option is used to select from one of three buzzer options. the first option is for both pins pa0 and pa1 to be used as normal i/os, the second option is for both pins to be configured as bz and bz buzzer pins, the third option selects only the pa0 pin to be used as a bz buzzer pin with the pa1 pin retaining its normal i/o pin function. note that the bz pin is the inverse of the bz pin which together generate a differential output which can supply more power to connected interfaces such as buzzers. the buzzer is driven by the internal clock source, which then passes through a divider, the division ratio of which is selected by configuration options to provide a range of buzzer frequencies from f s /2 2 to f s /2 9 . the clock source that generates f s , which in turn controls the buzzer frequency, can originate from three different sources, the external 32.768khz oscillator (lxt), the internal 32khz rc oscillator (lirc) or the system oscillator divided by 4 (f sys /4), the choice of which is determined by the f s clock source configuration option. note that the buzzer frequency is controlled by configuration options, which select both the source clock for the internal clock f s and the internal division ratio. there are no internal registers associated with the buzzer frequency. if the configuration options have selected both pins pa0 and pa1 to function as a bz and bz complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by setting bits pac0 and pac1 of the pac port control register to zero. the pa0 data bit in the pa data register must also be set high to enable the buzzer outputs, if set low, both pins pa0 and pa1 will remain low. in this way the single bit pa0 of the pa register can be used as an on/off control for both the bz and bz buzzer pin outputs. note that the pa1 data bit in the pa register has no control over the bz buzzer pin pa1. pa0/pa1 pin function control pac register pac0 pac register pac1 pa data register pa0 pa data register pa1 output function 001x pa0=bz pa1=bz 000x pa0=0 pa1=0 011x pa0=bz pa1=input line 010x pa0=0 pa1=input line 10xd pa0=input line pa1=d 11xx pa0=input line pa0=input line x stands for don t care d stands for data 0 or 1 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 87 december 2, 2011 ) )

) c & 7 ) % # ) % )

'
(
+ + h + = ) 2 ? 2 ? buzzer function
if configuration options have selected that only the pa0 pin is to function as a bz buzzer pin, then the pa1 pin can be used as a normal i/o pin. for the pa0 pin to function as a bz buzzer pin, pa0 must be setup as an output by setting bit pac0 of the pac port control register to zero. the pa0 data bit in the pa data register must also be set high to enable the buzzer output, if set low pin pa0 will remain low. in this way the pa0 bit can be used as an on/off control for the bz buzzer pin pa0. if the pac0 bit of the pac port control register is set high, then pin pa0 can still be used as an input even though the configuration option has configured it as a bz buzzer output. note that no matter what configuration option is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will override the configuration option selection and force the pin to always behave as an input pin. this arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the configuration option chosen; the actual function of the pin can be changed dynamically by the application program by programming the appropriate port control register bit. rev. 1.00 88 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces / $ 9 ' 2 ? $ 9 2 ? $ : $ : ' buzzer output pin control note: the above drawing shows the situation where both pins pa0 and pa1 are selected by configuration option to be bz and bz buzzer pin outputs. the port control register of both pins must have already been setup as output. the data setup on pin pa1 has no effect on the buzzer outputs.
interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are controlled by the action of the external int0, int1 and pint pins, while the internal interrupts are controlled by the timer/event counter overflows, the time base interrupt, the rtc interrupt, the sim (spi/i 2 c) interrupt, the a/d converter interrupt, the usb interrupt and smart card interrupt. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 89 december 2, 2011 $
$
'
!

0

! " n 5 ! 5 : ! ! 9
& ! ( 9 n 5 9 5 ! ! : ! 9
& ! ( : n 5 : 5 ! : ! " n 5 ! 5 9 ! % 3
2 n 5 2 5 ! $ '
/ n 5 5 ! $ & ' ( n 5 $ ' 5 ! 2
& ! ( + n 5 + 5 ! +
& ! ( * n 5 * 5 ! * ) 3 ! ! "
n 5 ! 5 ! 9
)
: n 5 5 : 5 ! 5 : 9 @ & + a n 5 9 5
)
9 n 5 5 9 5 : @ & + a n 5 : 5 ! 5 9 ! : n 5 ' 5 ' ! !
& ( n 5 ' 5 2 n 5 2 5 2 ! interrupt structure
interrupt registers overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the intc0, intc1, intc2, mfic0 and mfic1 registers, which are located in the data memory. by controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. intc0 register b i t76543210 name eif0 usbf crdf eei0 usbe crde emi r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit 7 unimplemented, read as 0 bit 6 eif0 : external interrupt 0 interrupt request flag 0: inactive 1: active bit 5 usbf : usb interrupt request flag 0: inactive 1: active bit 4 crdf : smart card interrupt request flag 0: inactive 1: active bit 3 eei0 : external interrupt 0 enable 0: disable 1: enable bit 2 usbe : usb interrupt enable 0: disable 1: enable bit 1 crde : smart card interrupt enable 0: disable 1: enable bit 0 emi : master interrupt global enable 0: disable 1: enable rev. 1.00 90 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
intc1 register b i t76543210 name cirf t1f t0f eif1 cire et1i et0i eei1 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7 cirf : smart card insertion/removal interrupt request flag 0: inactive 1: active bit 6 t1f : timer/event counter 1 interrupt request flag 0: inactive 1: active bit 5 t0f : timer/event counter 0 interrupt request flag 0: inactive 1: active bit 4 eif1 : external interrupt 1 request flag 0: inactive 1: active bit 3 cire : smart card insertion/removal interrupt enable 0: disable 1: enable bit 2 et1i : timer/event counter 1 interrupt enable 0: disable 1: enable bit 1 et0i : timer/event counter 0 interrupt enable 0: disable 1: enable bit 0 eei1 : external interrupt 1 interrupt enable 0: disable 1: enable intc2 register b i t76543210 name mf1f mf0f adf emf1i emf0i eadi r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 mf1f : multi-function 1 interrupt request flag 0: inactive 1: active bit 5 mf0f : multi-function 0 interrupt request flag 0: inactive 1: active bit 4 adf : a/d converter interrupt request flag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 emf1i : multi-function 1 interrupt enable 0: disable 1: enable bit 1 emf0i : multi-function 0 interrupt enable 0: disable 1: enable bit 0 eadi : a/d converter interrupt enable 0: disable 1: enable HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 91 december 2, 2011
mfic0 register b i t76543210 name pef tbf rtf sim0f epi etbi erti esim0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7 pef : external peripheral interrupt request flag 0: inactive 1: active bit 6 tbf : time base interrupt request flag 0: inactive 1: active bit 5 rtf : real time clock interrupt request flag 0: inactive 1: active bit 4 sim0f : sim 0 (spi/i 2 c) interrupt request flag 0: inactive 1: active bit 3 epi : external peripheral interrupt enable 0: disable 1: enable bit 2 etbi : time base interrupt enable 0: disable 1: enable bit 1 erti : real time clock interrupt enable 0: disable 1: enable bit 0 esim0 : sim 0 (spi/i 2 c) interrupt enable 0: disable 1: enable mfic1 register b i t76543210 name t3f t2f sim1f et3i et2i esim1 r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 t3f : timer/event counter 3 interrupt request flag 0: inactive 1: active bit 5 t2f : timer/event counter 2 interrupt request flag 0: inactive 1: active bit 4 sim1f : sim 1 (spi/i2c) interrupt request flag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 et3i : timer/event counter 3 interrupt enable 0: disable 1: enable bit 1 et2i : timer/event counter 2 interrupt enable 0: disable 1: enable bit 0 esim1 : sim 1 (spi/i2c) interrupt enable 0: disable 1: enable rev. 1.00 92 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
interrupt operation a timer/event counter overflow, time base, rtc overflow, spi/i2c data transfer complete, an end of a/d conversion, usb event, smart card event, smart card insertion/removal or the external interrupt line being triggered will all generate an interrupt request by setting their corresponding request flag. when this happens and if their appropriate interrupt enable bit is set, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. interrupt source priority vector smart card interrupt 1 04h usb interrupt 2 08h external interrupt 0 3 0ch external interrupt 1 4 10h timer/event counter 0 overflow 5 14h timer/event counter 1 overflow 6 18h smart card insertion/removal interrupt 7 1ch a/d converter interrupt 8 20h multi-function 0 interrupt 9 24h multi-function 1 interrupt 10 28h the sim0 interrupt, real time clock interrupt, time base interrupt and external peripheral inter - rupt share the same interrupt vector which is 24h while the sim1 interrupt, timer/event counter 2 overflow and timer/event counter 3 overflow interrupt share the same interrupt vector which is 28h. each of these interrupts has their own individual interrupt flag but also share the same multi-function interrupt flag named mf0f or mf1f respectively. the mf0f or mf1f flag will be cleared by hardware once the corresponding multi-function interrupt is serviced. however the indi - vidual interrupts that have triggered the multi-function interrupt need to be cleared by the applica - tion program. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 93 december 2, 2011
external interrupt for an external interrupt to occur, the global interrupt enable bit, emi, and external interrupt enable bits, eei0 and eei1, must first be set. additionally the correct interrupt edge type must be selected using the misc0 register to enable the external interrupt function and to choose the trigger edge type. an actual external interrupt will take place when the external interrupt request flag, eif0 or eif1, is set, a situation that will occur when a transition, whose type is chosen by the edge select bit, appears on the int0 or int1 pin. the external interrupt pins are pin-shared with the i/o pins pa0 and pa1 and can only be configured as external interrupt pins if their corresponding external interrupt enable bit in the intc0 or intc1 register has been set. the pin must also be setup as an input by setting the corresponding pac.0 and pac.1 bits in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 0ch or 10h, will take place. when the interrupt is serviced, the external interrupt request flags, eif0 or eif1, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on this pin will remain valid even if the pin is used as an external interrupt input. the misc0 register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising, falling or both rising and falling edge types can be chosen to trigger an external interrupt. note that the misc0 register can also be used to disable the external interrupt function. the external interrupt pins are connected to an internal filter to reduce the possibility of unwanted external interrupts due to adverse noise or spikes on the external interrupt input signal. as this internal filter circuit will consume a limited amount of power, the software control bits named int0flt and int1flt respectively in the rcflt register are provided to switch off the filter function, an option which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high. misc0 register b i t76543210 name crdcks1 crdcks0 smf smcen int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~6 crdcks1~crdcks0 : smart card interface clock source divided ratio selection 00: f crd =f m /2 01: f crd =f m /3 10: f crd =f m /1 11: f crd =f m /4 bit 5 smf : smart card clock output cclk frequency f cclk selection 0: f cclk =f crd /1 1: f cclk =f crd /2 bit 4 smcen : smart card interface clock control 0: f crd is disabled 1: f crd is enabled this bit is used to control the smart card interface clock source. if this bit is cleared to disable the clock, the relevant registers in the smart card interface module can not be accessed but will keep the original contents. when the smart card interface clock is disabled, it has no effect on the card insertion or removal detections. rev. 1.00 94 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces 5
& ) ) 6 5 % 6 : 5
6 9 5
! " 6 , 9 ! " 6 , : +
bit 3~2 int1s1~int1s0 : external interrupt 1 active edge selection 00: disabled 01: rising edge trigger 10: falling edge trigger 11: both rising and falling edges trigger bit 1~0 int0s1~int0s0 : external interrupt 0 active edge selection 00: disabled 01: rising edge trigger 10: falling edge trigger 11: both rising and falling edges trigger external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within the multi-function 0 interrupt. for an external peripheral interrupt to occur, the global interrupt enable bit, emi, external peripheral interrupt enable bit, epi, and multi-function 0 interrupt enable bit, emf0i, must first be set. an actual external peripheral interrupt will take place when the external interrupt request flag, pef, is set, a situation that will occur when a negative transition, appears on the pint pin. the external peripheral interrupt pin is pin-shared with one of the i/o pins, and is configured as a peripheral interrupt pin via the corresponding port control register bit. when the interrupt is enabled, the stack is not full and a negative transition type appears on the external peripheral interrupt pin, a subroutine call to the multi-function interrupt vector at location 24h, will take place. when the external peripheral interrupt is serviced, the emi bit will be cleared to disable other interrupts, however only the mf0f interrupt request flag will be reset. as the pef flag will not be automatically reset, it has to be cleared by the application program. timer/event counter interrupt for a timer/event counter 0 or timer/event counter 1 interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, et0i or et1i must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request flag, t0f or t1f is set, a situation that will occur when the timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter overflow occurs, a subroutine call to the timer interrupt vector at location 14h or 18h, will take place. when the interrupt is serviced, the timer interrupt request flag, t0f or t1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. timer event counter 0 and timer/event counter 1 have their own individual interrupt vectors. however the interrupt vector for timer/event counter 2 or timer/event counter 3 is contained within the multi-function 1 interrupt. for a timer/event counter 2 or a timer/event counter 3 interrupt to occur, the global interrupt enable bit, emi, timer/event counter 2 or timer/event counter 3 interrupt enable bit, et2i or et3i, and multi-function 1 interrupt enable bit, emf1i, must first be set. an actual interrupt will take place when the timer/event counter 2 or timer/event counter 3 request flag, t2f or t3f, is set, a situation that will occur when the timer/event counter 2 or timer/event counter 3 overflows. when the interrupt is enabled, the stack is not full and the timer/event counter 2 or timer/event counter 3 overflows, a subroutine call to the multi-function interrupt vector at location 28h, will take place. when the timer/event 2 or timer/event counter 3 interrupt is serviced, the emi bit will be cleared to disable other interrupts, however only the mf1f interrupt request flag will be reset. as the t2f or t3f flag will not be automatically reset, it has to be cleared by the application program. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 95 december 2, 2011
a/d interrupt for an a/d interrupt to be generated, the global interrupt enable bit emi and the a/d interrupt enable bit eadi must first be set. an actual a/d interrupt will take place when the a/d interrupt request flag, adf, is set, a situation that will occur when the a/d conversion process has finished. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d interrupt vector at location 20h, will take place. when the a/d interrupt is serviced, the a/d interrupt request flag adf will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. smart card interrupt for a smart card interrupt to be generated, the global interrupt enable bit emi must first be set as well as one of the associated smart card event interrupt enable bits. the smart card events that will generate an interrupt include situations such as a card voltage error, a card current overload, a waiting timer overflow, a parity error, a transmit buffer empty or an end of transmission or reception. once one of the associated smart card event interrupt enable control bits is set, it will automatically set the crde bit to 1 to enable the related smart card interrupt. an actual smart card interrupt will take place when the smart card interrupt request flag, crdf, is set, a situation that will occur when a smart card event has occurred. when the interrupt is enabled, the stack is not full and a smart card event has occurred, a subroutine call to the smart card interrupt vector at location 04h, will take place. when the smart card interrupt is serviced, the smart card interrupt request flag crdf will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. smart card insertion/removal interrupt for a smart card insertion/removal interrupt to be generated, the global interrupt enable bit emi and the smart card insertion/removal interrupt enable bit cire must first be set. an actual smart card insertion/removal interrupt will take place when the smart card insertion/removal interrupt request flag, cirf, is set, a situation that will occur when the smart card has been inserted or removed. when the interrupt is enabled, the stack is not full and the smart card has been inserted or removed, a subroutine call to the smart card insertion/removal interrupt vector at location 1ch, will take place. when the smart card insertion/removal interrupt is serviced, the smart card insertion/removal interrupt request flag cirf will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. sim (spi/i 2 c interface) interrupts the two sim (spi/i 2 c ) interrupts named sim0 interrupt and sim1 interrupt are contained within the multi-function 0 interrupt and multi-function 1 interrupt respectively. for an sim (spi/i 2 c interface) interrupt to occur, the global interrupt enable bit named emi, the associated sim interrupt enable control bit named esim0 or esim1 and the multi-function interrupt enable bit named emf0i or emf1i must be first set. an actual sim (spi/i 2 c interface) interrupt will take place when the sim (spi/i 2 c interface) request flag, sim0f or sim1f, is set, a situation that will occur when a byte of data has been transmitted or received by the spi/i 2 c interface or when an i 2 c address match occurs. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the spi/i 2 c interface or an i 2 c address match occurs, a subroutine call to the sim (spi/i 2 c interface) interrupt vector at location 24h or 28h respectively, will take place. when sim the interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the mf0f or mf1f interrupt request flag will be reset. as the sim request flag known as sim0f or sim1f will not be automatically reset, it has to be cleared by the application program. rev. 1.00 96 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
multi-function interrupt two additional interrupts known as the multi-function 0 interrupt and multi-function 1 interrupt are provided. unlike the other interrupts, the interrupt has no independent source, but rather is formed from several other existing interrupt sources. the multi-function 0 interrupt contains the sim0 interrupt, time base interrupt, real time clock interrupt, external peripheral interrupt while the multi-function 1 interrupt contains the sim1 interrupt, timer 2 overflow interrupt and timer 3 overflow interrupt. for a multi-function interrupt to occur, the global interrupt enable bit, emi, and the multi-function interrupt enable bit, emf0i or emf1i, must first be set. an actual multi-function interrupt will take place when the multi-function interrupt request flag, mf0f or mf1f, is set. this will occur when either a time base overflow, a real time clock overflow, sim0 or sim 1 interrupt, an external peripheral interrupt, timer 2 overflow interrupt or timer 3 overflow interrupt is generated. when the interrupt is enabled and the stack is not full, and either one of the interrupts contained within the multi-function interrupts occurs, a subroutine call to the multi-function interrupt vector at location 24h or 28h respectively will take place. when the interrupt is serviced, the multi-function request flag, mf0f or mf1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that the request flags from the original source of the multi-function interrupt, namely the time-base interrupt, real time clock interrupt, sim interrupts, external peripheral interrupt, timer 2 overflow interrupt or timer 3 overflow interrupt will not be automatically reset and must be manually reset by the application program. real time clock interrupt the real time clock interrupt is contained within the multi-function 0 interrupt. for a real time clock interrupt to be generated, the global interrupt enable bit, emi, real time clock interrupt enable bit, erti, and multi-function 0 interrupt enable bit, emf0i, must first be set. an actual real time clock interrupt will take place when the real time clock request flag, rtf, is set, a situation that will occur when the real time clock overflows. when the interrupt is enabled, the stack is not full and the real time clock overflows, a subroutine call to the multi-function 0 interrupt vector at location 24h, will take place. when the real time clock interrupt is serviced, the emi bit will be cleared to disable other interrupts, however only the mf0f interrupt request flag will be reset. as the rtf flag will not be automatically reset, it has to be cleared by the application program. similar in operation to the time base interrupt, the purpose of the rtc interrupt is also to provide an interrupt signal at fixed time periods. the rtc interrupt clock source originates from the internal clock source f s . this f s input clock first passes through a divider, the division ratio of which is selected by programming the appropriate bits in the rtcc register to obtain longer rtc interrupt periods whose value ranges from 28/f s ~215/f s . the clock source that generates f s , which in turn controls the rtc interrupt period, can originate from three different sources, the 32.768khz oscillator (lxt), the internal 32khz rc oscillator (lirc) or the system oscillator divided by 4 (f sys /4), the choice of which is determine by the f s clock source configuration option. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 97 december 2, 2011 ) )

) c & 7 % # % '
(
+ h + : 8
) + : + & ) h + : 8 & ) + : 9 rtc interrupt
note that the rtc interrupt period is controlled by both configuration options and an internal register rtcc. a configuration option selects the source clock for the internal clock f s , and the rtcc register bits rt2, rt1 and rt0 select the division ratio. note that the actual division ratio can be programmed from 2 8 to 2 15 . rtcc register b i t76543210 name lvdo qosc lvdc rt2 rt1 rt0 r/w r r/w r/w r/w r/w r/w por 000111 bit 7~6 unimplemented, read as 0 bit 5 lvdo : low voltage detector output 0: normal voltage 1: low voltage detected bit 4 qosc : rtc oscillator quick-start enable control 0: enable 1: disable bit 3 lvdc : low voltage detector enable control 0: disable 1: enable bit 2~0 rt2~rt0 : rtc interrupt period selection 000: 2 8 /f s 001: 2 9 /f s 010: 2 10 /f s 011: 2 11 /f s 100: 2 12 /f s 101: 2 13 /f s 110: 2 14 /f s 111: 2 15 /f s time base interrupt the time base interrupt is contained within the multi-function 0 interrupt. for a time base interrupt to be generated, the global interrupt enable bit, emi, time base interrupt enable bit, etbi, and multi-function 0 interrupt enable bit, emf0i, must first be set. an actual time base interrupt will take place when the time base interrupt request flag, tbf, is set, a situation that will occur when the time base overflows. when the interrupt is enabled, the stack is not full and the time base overflows, a subroutine call to the multi-function 0 interrupt vector at location 24h, will take place. when the time base interrupt is serviced, the emi bit will be cleared to disable other interrupts, however only the mf0f interrupt request flag will be reset. as the tbf flag will not be automatically reset, it has to be cleared by the application program. the purpose of the time base function is to provide an interrupt signal at fixed time periods. the time base interrupt clock source originates from the time base interrupt clock source originates from the internal clock source fs. this fs input clock first passes through a divider, the division ratio of which is selected by configuration options to provide longer time base interrupt periods. the time base interrupt time-out period ranges from 2 12 /f s ~2 15 /f s . the clock source that generates f s , which in turn controls the time base interrupt period, can originate from three different sources, the 32.768khz oscillator (lxt), the internal 32khz rc oscillator (lirc) or the system oscillator divided by 4 (f sys /4), the choice of which is determine by the f s clock source configuration option. rev. 1.00 98 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
essentially operating as a programmable timer, when the time base overflows it will set a time base interrupt flag which will in turn generate an interrupt request via the multi-function 0 interrupt vector. programming considerations by disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the intc0, intc1, intc2, mfic0 and mfic1 registers until the corresponding interrupt is serviced or until the request flag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request flag changes from low to high. if it is required to prevent a certain interrupt from waking up the micro controller then its respective request flag should be first set high before entering the sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 99 december 2, 2011 ) )

) c & 7 % # % )

'
(
+ : + h + : 8 )
2 + : + & ) h + : 8 & ) time base interrupt
reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. rev. 1.00 100 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces ! 4 ' '

9 , = 4 ' ' ' power-on reset timing chart
more information regarding external reset circuits is located in application note ha0075e on the holtek website. res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initiated from this point. low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. one of a range of specified voltage values for v lvr can be selected using configuration options. the v lvr value will be selected as a pair in conjunction with a low voltage detect value. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 101 december 2, 2011 !

9 , = 4 ' ' 9 , 7 4 ' ' ' res reset timing chart ! & - 9 , : h : 5 : 9 / h : 9 9 / 4 ' ' 4 9 , 9 : 5 l l 4 ' ' : 6 7 : 7 l * 9 9 l note: * it is recommended that this component is added for added esd protection ** it is recommended that this component is added in environments where power line noise is significant external res circuit % 4

' low voltage reset timing chart
watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1 . watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are af - fected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack rev. 1.00 102 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces '

' wdt time-out reset during normal operation timing chart '

wdt time-out reset during power down timing chart
the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register reset (power-on) res reset (normal operation) wdt time-out (normal operation) wdt time-out (halt) usb reset (normal) usb reset (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu rtcc 00 0111 00 0111 00 0111 uu uuuu 00 0111 00 0111 status 00 xxxx uu uuuu 1u uuuu 11 uuuu uu uuuu 01 uuuu tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu misc0 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 misc1 0000 1010 0000 1010 0000 1010 uuuu uuuu 0000 1010 0000 1010 clkmod 0000 0x11 0000 0x11 0000 0x11 uuuu uuuu 0000 0x11 0000 0x11 dc2dc 00 00 00 uu 00 00 intc0 000 0000 000 0000 000 0000 uuu uuuu 000 0000 000 0000 intc1 000 0000 000 0000 000 0000 uuu uuuu 000 0000 000 0000 intc2 00 00 00 00 00 00 uu uu 00 00 00 00 mfic0 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 mfic1 000 000 000 000 000 000 uuu uuu 000 000 000 000 pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 papu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pa 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pb 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcpu 000 0000 000 0000 000 0000 uuuu uuuu 000 0000 000 0000 pc 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pd 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pe 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pec 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pfpu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pf 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pfc 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pwm0l 0000 0 0000 0 0000 0 uuuu u 0000 0 0000 0 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 103 december 2, 2011
register reset (power-on) res reset (normal operation) wdt time-out (normal operation) wdt time-out (halt) usb reset (normal) usb reset (halt) pwm0h 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwm1l 0000 0 0000 0 0000 0 uuuu u 0000 0 0000 0 pwm1h 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwm2l 0000 0 0000 0 0000 0 uuuu u 0000 0 0000 0 pwm2h 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwm3l 0000 0 0000 0 0000 0 uuuu u 0000 0 0000 0 pwm3h 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tmr0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr0c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu 00 0 1000 00 0 1000 tmr1h xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr1l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr1c 0000 1 0000 1 0000 1 uuuu u 0000 1 0000 1 tmr2 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr2c 0 0 0 1000 00 0 1000 00 0 1000 uu u uuuu 00 0 1000 00 0 1000 tmr3 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr3c 0 0 0 1000 00 0 1000 00 0 1000 uu u uuuu 00 0 1000 00 0 1000 ledctrl 000 0000 000 0000 000 0000 uuu uuuu 000 0000 000 0000 lcdctrl 0 00 0000 0 00 0000 0 00 0000 u uu uuuu 0 00 0000 0 00 0000 lcdio 000 000 000 uuu 000 000 rcflt 00 0000 00 0000 00 0000 uu uuuu 00 0000 00 0000 adrl xxxx xxxx xxxx uuuu xxxx xxxx adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx adcr 01 000 01 000 01 000 uuu uu 01 000 01 000 acsr 1100 0000 1100 0000 1100 0000 uuuu uuuu 1100 0000 1100 0000 adpcr 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sim0ctl0 1110 000 1110 000 1110 000 uuuu uuuu 1110 000 1110 000 sim0ctl1 1000 0001 1000 0001 1000 0001 uuuu uu u 1000 0001 1000 0001 sim0dr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx sim0ar/sim0ctl2 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sim1ctl0 1110 000 1110 000 1110 000 uuuu uuuu 1110 000 1110 000 sim1ctl1 1000 0001 1000 0001 1000 0001 uuuu uu u 1000 0001 1000 0001 sim1dr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx sim1ar/sim1ctl2 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 dal 0000 0000 0000 uuuu 0000 0000 dah 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 dactrl x x x 0 xxx 0 xxx 0 uuu u xxx 0 xxx 0 ccr 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 csr 1000 0000 1000 0000 1000 0000 uuuu uuuu 1000 0000 1000 0000 cccr 00xx x0x0 00xx x0x0 00xx x0x0 uuxx xuxu 00xx x0x0 00xx x0x0 cetu1 0 001 0 001 0 001 u uuu 0 001 0 001 cetu0 0111 0100 0111 0100 0111 0100 uuuu uuuu 0111 0100 0111 0100 cgt1 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 cgt0 0000 1100 0000 1100 0000 1100 uuuu uuuu 0000 1100 0000 1100 rev. 1.00 104 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
register reset (power-on) res reset (normal operation) wdt time-out (normal operation) wdt time-out (halt) usb reset (normal) usb reset (halt) cwt2 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 cwt1 0010 0101 0010 0101 0010 0101 uuuu uuuu 0010 0101 0010 0101 cwt0 1000 0000 1000 0000 1000 0000 uuuu uuuu 1000 0000 1000 0000 cier 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 cipr 0 00 0000 0 00 0000 0 00 0000 u uu uuuu 0 00 0000 0 00 0000 ctxb 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 crxb 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 usc 1 00 0000 1 00 0000 u uu uuuu u uu uuuu u 00 0100 u 00 0100 usr 00 0000 00 0000 uu uuuu uu uuuu 00 0000 00 0000 ucc 0 0 0000 0 0 0000 u u uuuu u u uuuu u 0 u000 u 0 u000 awr 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 stall 11 1110 11 1110 uu uuuu uu uuuu 11 1110 11 1110 sies 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 umisc 0 x x 000 0xx 000 uxx uuu uxx uuu 000 000 000 000 setio 11 1110 11 1110 uu uuuu uu uuuu 11 1110 11 1110 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo4 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo5 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uic 00 0000 00 0000 uu uuuu uu uuuu 00 0000 00 0000 ntim 00 0000 00 0000 uu uuuu uu uuuu 00 0000 00 0000 pipe 00 000 00 000 uu uuu uu uuu 00 000 00 000 note: u stands for unchanged x stands for unknown stands for unimplemented HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 105 december 2, 2011
oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. six types of system clocks can be selected while various clock source options are provided for maximum flexibility. all oscillator options are selected through the configuration options. system clock configurations there are many ways of generating the system clock, three high speed oscillators and two low speed oscillators supplied clock. an external clock source can also be used as the system clock. the three high speed oscillators are the external crystal/ceramic oscillator (hxt), the external rc network (erc) and the internal high speed rc oscillator (hirc). the two low speed oscillators are the external 32.768khz crystal oscillator (lxt) and the internal 32khz rc oscillator (lirc). selecting whether the low frequency or high oscillator is used as the system oscillator is implemented using the hlclk bit in the clkmod register. the source clock for the high speed oscillator is chosen via configuration options as well as the low speed oscillator. the frequency of the slow clock is also determined using the slowc0~slowc2 bits in the clkmod register. external crystal/ ceramic oscillator hxt after selecting the external crystal configuration option, the simple connection of a crystal across osc1 and osc2, is normally all that is required to create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specification. in most applications, resistor r p1 is not required, however for those applications where the lvr function is not used, r p1 may be necessary to ensure the oscillator stops running when vdd falls below its operating range. the internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pins. an additional configuration option must be setup to configure the device according to whether the oscillator frequency is high, defined as equal to or above 1mhz, or low, which is defined as below 1mhz. more information regarding oscillator applications is located on the holtek website. crystal oscillator c1 and c2 values crystal frequency c1 c2 20mhz 12mhz 8mhz 4mhz 1mhz 455khz (see note 2) 10pf 10pf note: 1. c1 and c2 values are for guidance only. 2. xtal mode configuration option: 455khz. 3. r p1 =5m
~10m
is recommended. crystal recommended capacitor values rev. 1.00 106 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces + : + : : crystal/ceramic oscillator
external rc oscillator erc using the erc oscillator only requires that a resistor, with a value between 47k
and 1.5m
,is connected between osc1 and vdd, and a 470pf capacitor is connected between osc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an external 150k
resistor connected and with a 5v voltage power supply and temperature of 25 c degrees, the oscillator will have a frequency of 4mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pc0, leaving pin pc1 free for use as a normal i/o pin. note that an internal capacitor together with the external resistor, r osc , are the components which determine the frequency of the oscillator. the external capacitor shown on the diagram does not influence the frequency of oscillation. this external capacitor should be added to improve oscillator stability if the open-drain osc2 output is utilised in the application circuit. the internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pins. internal rc oscillator hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fixed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25j degrees, the fixed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pc0 and pc1 are free for use as normal i/o pins. internal 32khz rc oscillator lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via configuration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the oscillation frequency of 32khz will have a frequency range from 28.1khz to 34.4khz. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 107 december 2, 2011 : : &
7 - 9 5 4 ' ' external rc oscillator erc * + / 0 1
) % internal rc oscillator lirc
external 32.768khz oscillator lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via configuration option. this clock source has a fixed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins osc3 and osc4. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specification. the external parallel feedback resistor, rp, is required. some configuration options determine if the osc3/osc4 pins are used for the lxt oscillator or as i/o pins. if the lxt oscillator is not used for any clock source, the osc3/osc4 pins can be used as normal i/o pins. if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the osc3/osc4 pins. lxt oscillator c3 and c4 values crystal frequency c3 c4 32768hz 8pf 10pf note: 1. c3 and c4 values are for guidance only. 2. r p2 =5m~10m
is recommended. 32.768khz crystal recommended capacitor values rev. 1.00 108 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces 7 * 7 * + * + - . 0 1 * + , - . / 0 1 crystal/ceramic oscillator
lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the qosc bit in the rtcc register. qosc bit lxt mode 0 quick start 1 low-power after power on, the qosc bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the qosc bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the qosc bit high about 2 seconds after power-on. it should be noted that, no matter what condition the qosc bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low-power mode. external oscillator ec the system clock can also be supplied by an externally supplied clock giving users a method of synchronizing their external hardware to the microcontroller operation. this is selected using a configuration option and supplying the clock on pin osc1. pin osc2 can be used as a normal i/o pin if the external oscillator is used. the internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pin. however, as the filter circuit consumes a certain amount of power, an oscillator configuration option exists to turn this filter off. not using the internal filter should be considered in power sensitive applications and where the externally supplied clock is of a high integrity and supplied by a low impedance source. system operating modes the device has the ability to operate in several different modes. this range of operating modes, known as normal mode, slow mode, idle mode and sleep mode, allow the device to run using a wide range of different slow and fast clock sources. the devices also possess the ability to dynamically switch between different clocks and operating modes. with this choice of operating functions users are provided with the flexibility to ensure they obtain optimal performance from the device according to their application specific requirements. clock sources in discussing the system clocks for the device, they can be seen as having a dual clock mode. these dual clocks are what are known as a high oscillator and the other as a low oscillator. the high and low oscillator are the system clock sources and can be selected dynamically using the hlclk bit in the clkmod register. the high oscillator has the internal name f m whose source is selected using a configuration option from a choice of either an external crystal/resonator, external rc oscillator or external clock source. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 109 december 2, 2011
clkmod register b i t76543210 name slowc2 slowc1 slowc0 simidle lto hto idlen hlclk r/w r/w r/w r/w r r r/w r por00000000 bit 7~5 slowc2~slowc0 : low speed clock frequency f slow selection 000: f sl 001: f sl 010: f m /64 011: f m /32 100: f m /16 101: f m /8 110: f m /4 111: f m /2 bit 4 simidle : simn (spi/i 2 c) continues running in idle mode control 0: disable 1: enable bit 3 lto : low speed oscillator ready flag 0: non-time-out 1: time-out bit 2 hto : high speed oscillator ready flag 0: non-time-out 1: time-out bit 1 idlen : idle mode control 0: disable (sleep mode) 1: enable (idle mode) bit 0 hlclk : system clock frequency f sys selection 0: f m 1: f slow the low oscillator clock source has the internal name f sl , whose source is also selected by configu- ration option from a choice of either an external 32.768khz oscillator (lxt) or the internal 32khz rc oscillator (lirc). this internal f sl ,f m clock, is further modified by the slowc0~ slowc2 bits in the clkmod register to provide the low frequency clock source f slow . an additional sub internal clock, with the internal name f sub , is a 32khz clock source which can be sourced from either the internal 32k_int oscillator or an external 32768 hz crystal, selected by configuration option. together with f sys /4, it is used as a clock source for certain internal functions such as the lcd driver, watchdog timer, buzzer, rtc interrupt and time base interrupt. the lcd clock source is the f sub clock source divided by 8, giving a frequency of 4khz. the internal clock f s ,is simply a choice of either f sub or f sys /4, using a configuration option. rev. 1.00 110 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 111 december 2, 2011 , ) - 3 / 0 $ % o i ' % ! 6 i k 9 0 $ % o i ' % ! 6 i k : 3 / 3 / 0 $ % o i ' % ! 6 i k : 0 $ % o i ' % ! 6 i k 9 3 / i 0 % % ; i i 0 % % ; i . / . 0 " - % 1 2 0 3 ) # - % 3 ) 4 - 5 . 6 . 7 1 1 8 ( % 3 9 , 5 ) e % # % e ) c k ) ' ) " - ) ) ) e % # % l e ) c k ) ) ( - ) - ) ) ) e % # % e ) c k ) ) ' ) : - ) & ) ) e % # % e ) c k ) & + h ) & . 7 % # % p dual clock mode operation # ) % 0 % % ; 2
) c ) # ) % # ) % 3 / % 9 % # ) % )

% : % + ) & + e , , , ) & . 7 e ) % # # ) ) c & 7 ) 2 ) c & 7 ) 2
: : ) / )

) 2 ) % ' k ) 2 & % '
e
2
e 2 1 1 e ' % % 3
* 7 ! 0 # # ) 0 # & ! & 0 & ! )

0

: : + 5
! " / 5
) ) )

! : 0 dual clock mode structure
operating modes after the correct clock source configuration selections are made, overall operation of the chosen clock is achieved using the clkmod register. a combination of the hlclk and idlen bits in the clkmod register and use of the halt instruction determine in which mode the device will be run. the devices can operate in the following modes. normal mode f m on, f slow on, f sys =f m , cpu on, f s on, f lcd on/off depending upon the lcden bit, f wdt on/off depending upon the wdt configuration option and wdt control register. slow mode0 f m off, f sys =f slow ,f slow =f sl =f lirc or f lxt , cpu on, f s on, f lcd on/off depending upon the lcden bit, f wdt on/off depending upon the wdt configuration option and wdt control register. slow mode1 f m on, f sys =f slow =f m /2~f m /64, cpu on, f s on, f lcd on/off depending upon the lcden bit, f wdt on/off depending upon the wdt configuration option and wdt control register. idle mode fm, f slow ,f sys off, cpu off; f sub on, f s on/off by selecting f sub or f sys /4, f lcd on/off depending upon the lcden bit, f wdt on/off depending upon the wdt configuration option and wdt control register. the idle mode is determined by the idle mode control bit named idlen in the clkmod register when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. sleep mode f m ,f slow ,f sys ,f s ,f lcd off, cpu off; f sub ,f wdt on/off depending upon the wdt configuration option and wdt control register. the sleep mode is determined by setting the idle mode control bit named idlen to 0 when the halt instruction is executed. operation mode description cpu f sys f sub f s f lcd normal mode on f m on on on/off (4) slow 0 mode on f slow =f lirc or f lxt on on on/off (4) slow 1 mode on f slow =f m /2~f m /64 on on on/off (4) idle mode off off (1) on on/off (3) on/off (4) sleep mode off off on/off (2) off (3) off note: 1. in the idle mode, the f sys clock on/off function is determined by whether the simidle bit set to 1 or 0 respectively and can only be used for the master spi operation or pclk output for which the clock source comes from the f sys clock. 2. in the sleep mode the f sub clock on/off function is determined by whether the wdt is enabled or disabled respectively. 3. the f s clock on/off function in the idle or sleep mode is determined by whether the selected clock source of the wdt function is f sub or the f sys /4 clock. 4. the f lcd clock turned on/off function is determined by the lcden or leden control bit. rev. 1.00 112 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
power down mode and wake-up power down mode all of the holtek microcontroller have the ability to enter a power down mode. when the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. this occurs because when the device enters the power down mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in application areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruction in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the watchdog timer internal oscillator. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 113 december 2, 2011
if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 before entering the power down mode, the wake-up function of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended. low voltage detector lvd the low voltage detect internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the dc characteristics. lvd operation the lvd function must be first enabled via a configuration option after which bits 3 and 5 of the rtcc register are used to control the overall function of the lvd. bit 3 is the enable/disable control bit and is known as lvdc, when set low the overall function of the lvd will be disabled. bit 5 is the lvd detector output bit and is known as lvdo. under normal operation, and when the power supply voltage is above the specified vlvd value in the dc characteristic section, the lvdo bit will remain at a zero value. if the power supply voltage should fall below this v lvd value then the lvdo bit will change to a high value indicating a low voltage condition. note that the lvdo bit is a read-only bit. by polling the lvdo bit in the rtcc register, the application program can therefore determine the presence of a low voltage condition. after power-on, or after a reset, the lvd will be switched off by clearing the lvdc bit in the rtcc register to zero. note that if the lvd is enabled there will be some power consumption associated with its internal circuitry, however, by clearing the lvdc bit to zero the power can be minimised. it is important not to confuse the lvd with the lvr function. in the lvr function an automatic reset will be generated by the microcontroller , whereas in the lvd function only the lvdo bit will be affected with no influence on other microcontroller functions. there are a range of voltage values, selected using a configuration option, which can be chosen to activate the lvd. rev. 1.00 114 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. it operates by providing a device reset when the watchdog timer counter overflows. watchdog timer operation the watchdog timer clock source is provided by the internal clock, f s , which is in turn supplied by one of two sources selected by configuration option: f sub or f sys /4. note that if the watchdog timer configuration option has been disabled, then any instruction relating to its operation will result in no operation. most of the watchdog timer options, such as enable/disable, watchdog timer clock source and clear instruction type are selected using configuration options. in addition to a configuration option to enable the watchdog timer, there are four bits, wdten3~ wdten0, in the misc1 register to offer an additional enable control of the watchdog timer. these bits must be set to a specific value of 1010 to disable the watchdog timer. any other values for these bits will keep the watchdog timer enabled. after power on these bits will have the disabled value of 1010. one of the wdt clock sources is the internal fsub, which can be sourced from either the internal 32khz rc oscillator (lirc) or the external 32.768khz oscillator (lxt). the lirc oscillator has an approximate period of 31.2ms at a supply voltage of 5v. however, it should be noted that this specified internal clock period can vary with v dd , temperature and process variations. the lxt oscillator is supplied by an external 32768hz crystal. the other watchdog timer clock source option is the f sys /4 clock. whether the watchdog timer clock source is it s the lirc, the lxt oscillator or f sys /4, it is divided by 2 13 ~2 16 , using configuration option to obtain the required watchdog timer time-out period. the max time out period is when the 2 16 option is selected. this time-out period may vary with temperature, vdd and process variations. as the clear instruction only resets the last stage of the divider chain, for this reason the actual division ratio and corresponding watchdog timer time-out can vary by a factor of two. the exact division ratio depends upon the residual value in the watchdog timer counter before the clear instruction is executed. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 115 december 2, 2011 ' )

%
% ' : 5 % ' + 5 : +

'
(
) 2 % '
@ + : * & ) e + : 7 & ) e + : 8 & ) + : . & ) a + -
) & + ) & + : + e ) & + : * e ) & + : 7 ) & + : 8 )

% # % ) % # ) % watchdog timer
misc1 register b i t76543210 name ode3 ode2 ode1 ode0 wdten3 wdten2 wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00001010 bit 7~4 ode3 ~ode0: pa3~pa0 open drain control described in input/output port section bit 3~0 wdten3, wdten2, wdten1, wdten0 : wdt function enable 1010: wdt disabled other values: wdt enabled recommended value is 0101 if the watchdog timer enable configuration option is selected, then the watchdog timer will al ways be enabled and the wdten3 ~ wdten0 control bits will have no effect. the wdt is only disabled when both the wdt configuration option is disabled and when bits wdten3 ~ wdten0?1010. the wdt is enabled when either the wdt configuration option is enabled or when bits wdten3 ~ wdten0 1010 if the f sys /4 clock is used as the watchdog timer clock source, it should be noted that when the sys - tem enters the power down mode, then the instruction clock is stopped and the watchdog timer will lose its protecting purposes. for systems that operate in noisy environments, using the lirc os - cillator is strongly recommended. under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the power down mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a halt instruction. clearing the watchdog timer there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the single clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the watchdog timer. note that for this second option, if clr wdt1 is used to clear the watchdog timer, successive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the watchdog timer. similarly after the clr wdt2 instruction has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. rev. 1.00 116 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
usb interface the devices contains an embedded usb module, which is a 4-wire serial bus that allows communication with an external host device. a token based protocol method is used by the host device for communication control. other advantages of the usb bus include live plugging and unplugging and dynamic device configuration. it is particularly suitable for the devices with data links between pcs or peripheral devices, or the devices with usb interface such as usb mice, usb keyboards or usb joysticks, etc. as the complexity of usb data protocol does not permit comprehensive usb operation information to be provided in this datasheet, the reader should therefore consult other external information for a detailed usb understanding. usb operation to communicate with an external usb host, the internal usb module has external pins known as dp and dm along with the 3.3v regulator output v33o. the usb module has 6 endpoints and a 160 byte fifo for the endpoints respectively. a serial interface engine (sie) decodes the incoming usb data stream and transfers it to the correct endpoint buffer memory (fifo). a series of status registers provide the user with the usb data transfer situation as well as any error conditions. the usb contains its own independent interrupt which can be used to indicate when the usb fifos are accessed by the host device or a change of the usb operating conditions including the usb suspend mode, resume event or usb reset occurs. usb status and control registers there are several registers associated with the usb function. some of the registers control the overall function of the usb module as well as the interrupts, while some of the registers contain the status bits which indicate the usb data transfer situations and error condition. also there are fifos for the usb endpoints to store the data received from or to be transmitted to the usb host. the usb module has 6 endpoints (ep0~ep5) with a different fifo size for each one. the fifo size is 8 bytes for ep0~ep2 and ep4 which support interrupt transfer , while the fifo size for ep3 and ep5 is 64 bytes which can support bulk transfer . HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 117 december 2, 2011
usb register summary address name por state bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 60h usc 1-00 0000 urd pll v33c resume urst rmwk susp 61h usr --00 0000 ep5if ep4if ep3if ep2if ep1if ep0if 62h ucc -0-0 0000 sysclk susp2 usbcken eps2 eps1 eps0 63h awr 0000 0000 uad6 uad5 uad4 uad3 uad2 uad1 uad0 wken 64h stall --11 1110 stl5 stl4 stl3 stl2 stl1 stl0 65h sies 0000 0000 nmi crcf nak in out err aset 66h umisc 0xx- -000 len0 ready setcmd clear tx request 67h setio --11 1110 setio5 setio4 setio3 setio2 setio1 setio0 68h fifo0 xxxx xxxx data for endpoint 0 69h fifo1 xxxx xxxx data for endpoint 1 6ah fifo2 xxxx xxxx data for endpoint 2 6bh fifo3 xxxx xxxx data for endpoint 3 6ch fifo4 xxxx xxxx data for endpoint 4 6dh fifo5 xxxx xxxx data for endpoint 5 6eh unused, read as 0 6fh unused, read as 0 70h uic --00 0000 eu5i eu4i eu3i eu2i eu1i eu0i 71h ntim --00 0000 nti5m nti4m nti3m nti2m nti1m nti0m 72h pipe --00 000- ep5e ep4e ep3e ep2e ep1e usc register the usc register contains the status bits for usb suspend, resume and reset indications. it also contains the bits used to control the remote wake-up, v33o output, pll function and usb reset behavior. further explanation on each bit is given below: b i t76543210 name urd pll v33c resume urst rmwk susp r/w r/w r/w r/w r r r/w r por10000000 bit 7 urd : usb reset signal control 0: usb reset signal can not reset the mcu 1: usb reset signal will reset the mcu bit 6 unimplemented, read as 0. bit 5 pll : pll enable control 0: turn on the pll 1: turn off the pll bit 4 v33c : v33o output enable control 0: turn off the v33o output 1: turn on the v33o output rev. 1.00 118 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
bit 3 resume : usb resume indication flag 0: usb device does not receive the resume signal or has left the suspend mode. 1: usb device receives the resume signal and is going to leave the suspend mode. when the usb device receives the resume signal, this bit is set to 1 by sie. this bit will appear for about 20ms, waiting for the mcu to detect it. when the resume is set by sie, an interrupt will be generated to wake up the mcu. in order to detect the suspend state, mcu should set the usbcken bit to 1 and clear the pll bit to 0 to enable the sie functions. the resume bit will be cleared when the susp bit is set to 0 . when the mcu detects the suspend mode susp, the resume signal resume which causes mcu to wake up should be remembered and taken into consideration. bit 2 urst : usb reset indication flag 0: no usb reset event occurred. 1: usb reset event has occurred. the usb bit is set and cleared by usb sie. when the urst bit is set to 1 , it indicates that a usb reset event has occurred and a usb interrupt will be initiated. bit 1 rmwk : usb remote wake-up command 0: disable usb remote wake-up command 1: initiate usb remote wake-up command the rmwk is set to 1 by mcu to force the usb host leaving the suspend mode. set rmwk bit to 1 to initiate the remote walk-up command. when the rmwk bit is set to 1,a2 s delay for clearing this bit to 0 is necessary to ensure that the rmwk command is accepted by the sie. bit 0 susp : usb suspend indication flag 0: usb leaves the suspend mode. 1: usb enters the suspend mode. this bit is read only and set to 1 by sie to indicate that the usb bus enters the suspend mode. the usb interrupt is also generated when the susp bit is asserted. usr register the usr (usb endpoint interrupt status register) register is consisted of the endpoint request flags (ep0if~ep5if) used to indicate which endpoint is accessed. when an endpoint is accessed, the related endpoint request flag will be set to 1 by sie and a usb interrupt will be generated if the control bits related to the usb interrupt are enabled and the stack in the host mcu is not full. when the active endpoint request flag is serviced, the endpoint request flag has to be cleared to 0 by application program. b i t76543210 name ep5if ep4if ep3if ep2if ep1if ep0if r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 unimplemented, read as 0. bit 5~0 ep5if~ep0if : endpoint interrupt request flags 0: the corresponding endpoint is not accessed. 1: the corresponding endpoint has been accessed. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 119 december 2, 2011
ucc register the ucc register is the system clock control register implemented to select the clock used by the mcu. this register consists of usb clock control bit usbcken, second suspend mode control bit susp2 and system clock selection bit sysclk. this register is also used to select which endpoint fifo is accessed by endpoint fifo selection bits eps2~eps0. further explanation on each of the bits is given below: b i t76543210 name sysclk susp2 usbcken eps2 eps1 eps0 r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 unimplemented, read as 0. bit 6 sysclk : system clock input selection 0: 12mhz clock is used 1: 6mhz clock is used this bit is used to specify the system clock oscillator frequency used by the mcu. if a 6mhz crystal oscillator or resonator is used, this bit should be set to 1 . if a 12mhz crystal oscillator or resonator is used, this bit should be set to 0. bit 5 unimplemented, read as 0. bit 4 susp2 : suspend mode 2 control 0: optimized setting in suspend mode 1: test setting in suspend mode. the band-gap circuit is turned off. it is strongly recommended that this bit should be set to 0 when the usb interface is in suspend mode. otherwise, the unpredictable results will occur. bit 3 usbcken : usb clock enable control 0: usb clock is disabled 1: usb clock is enabled when the usb device receives the suspend signal sent from the usb host, the usb clock enable control bit usbcken should be set to 0 to reduce the power consumption. bit 2~0 eps2~eps0 : endpoint fifo selection 000: endpoint 0 fifo is selected 001: endpoint 1 fifo is selected 010: endpoint 2 fifo is selected 011: endpoint 3 fifo is selected 100: endpoint 4 fifo is selected 101: endpoint 5 fifo is selected 11x: reserved for further expansion and can not be used. the eps2~eps0 bits are used to select which endpoint is to be accessed. if the selected endpoint does not exist, the related functions are not available. awr register the awr register contains the usb device address and the remote wake-up function control bit. the initial value of the usb device address is 00h. the address value extracted from the usb command is to be immediately loaded into this register or not depending upon the device address update control bit aset in the sies register. b i t76543210 name uad6 uad5 uad4 uad3 uad2 uad1 uad0 wken r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~1 uad6~uad0 : usb device address bit 0 wken : usb device remote wake-up function enable control 0: disable usb remote wake-up function 1: enable usb remote wake-up function rev. 1.00 120 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
stall register the stall register shows whether the corresponding endpoint works properly or not. as soon as the endpoint works improperly, the related bit in the stall register has to be set to 1 by application program. the contents of the stall register will be cleared by usb reset signal. b i t76543210 name stl5 stl4 stl3 stl2 stl1 stl0 r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 unimplemented, read as 0. bit 5~0 stl5~stl0 : usb endpoint stall indication 0: the corresponding usb endpoint is not stalled. 1: the corresponding usb endpoint is stalled. the stl bit is set by users when the related usb endpoint is stalled. these bits are cleared by usb reset signal. for endpoint 0 the stall bit stl0 can also be cleared by setup token event. sies register the sies register is used to indicate the present signal state which the sie receives and also control whether the sie changes the device address automatically or not. b i t76543210 name nmi crcf nak in out err aset r/w r/w r r/w r r r/w r/w r/w por00000000 bit 7 nmi : nak token interrupt global mask control 0: usb nak token interrupt for all endpoints is masked. 1: usb nak token interrupt depends upon the individual mask control bits in ntim register. if this bit is cleared to 0 , the interrupt will not occur when the device sends a nak token to the usb host. otherwise, when this bit is set to 1 and the device sends a nak token to the usb host, the nak token interrupt will be generated or not depending upon the nak token interrupt mask control bit ntixm (x=0~5) in ntim register. bit 6 unimplemented, read as 0. bit 5 crcf : error indication flag during transfer 0: no usb transfer error occurs. 1: usb transfer error has occurred. the error conditions include crc, pid and incomplete token errors. the crcf bit is set by hardware and is necessary to be cleared by firmware. bit 4 nak : nak signal indication flag 0: no nak signal is transmitted. 1: nak signal has been transmitted. the nak bit is used to indicate that the sie has transmitted a nak signal to the usb host in response to the usb host in or out token when the endpoint was accessed. bit 3 in : in token indication flag for endpoint 0 0: the received token packet is not in token. 1: the received token packet is in token. the in bit is used to indicate that for the usb endpoint 0 the current received signal from the usb host is in token. bit 2 out : out token indication flag for endpoint 0 0: the received token packet is not out token. 1: the received token packet is out token. the out bit is used to indicate that for the usb endpoint 0 the current received signal from the usb host is out token except for the out zero length token. the firmware clears this bit after the out data has been read. also, this bit will be cleared by sie after the next valid setup token is received. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 121 december 2, 2011
bit 1 err : error indication flag during endpoint 0 fifo is accessed 0: no error occurs during endpoint 0 fifo is accessed. 1: error has occurred during endpoint 0 fifo is accessed. the err bit is used to indicate that there are some errors occurred during endpoint 0 fifo is accessed. this bit is set by sie and should be cleared by firmware. bit 0 aset : device address update control 0: device address is updated immediately when the awr register is written. 1: device address is updated after the device in token data has been read (setup stage finished). the aset bit is used to configure the sie to automatically update the device address with the value stored in the awr register. when this bit is set to 1 by firmware, the sie will update the device address with the value stored in the awr register after the usb host has successfully read the data from the device by in token. otherwise, when this bit is cleared to 0 , the sie will update the device address immediately after an address is written to the awr register. umisc register the umisc register contains the commands to control the desired endpoint fifo action along with the status to show the condition of the desired endpoint fifo. the umisc register will be cleared by a usb reset signal. b i t76543210 name len0 ready setcmd clear tx request r/w r/w r r/w r/w r/w r/w por0xx00000 x means unknown. bit 7 len0 : zero-length packet indication flag for endpoint 0 0: no operation. 1: a zero-length packet is sent from the usb host. if this bit is set to 1, it indicates that a 0-sized packet is sent from a usb host. this bit should be cleared by the application program or by the next valid setup token. bit 6 ready : endpoint fifo ready indication flag 0: the desired endpoint fifo is not ready. 1: the desired endpoint fifo is ready. this bit is used to indicate whether the desired endpoint fifo is ready to operate or not. bit 5 setcmd : setup command indication flag 0: the data in the endpoint 0 fifo is not setup token. 1: the data in the endpoint 0 fifo is setup token. this bit is used to indicate whether the data in the endpoint 0 fifo is setup token or not. it is set by hardware and cleared by firmware. bit 4~3 unimplemented, read as 0. bit 2 clear : clear requested fifo 0: no operation. 1: clear the requested endpoint fifo. this bit is used by mcu to clear the requested fifo, even if the fifo is not ready. if user wants to clear the current requested endpoint fifo, the clear bit should be set to 1 to generate a positive pulse with 2 s pulse width and then clear this bit to zero. rev. 1.00 122 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
bit 1 tx : direction of data transfer between the mcu and the endpoint fifo 0: the data transfer from the endpoint fifo to the mcu (mcu read data from the endpoint fifo). 1: the data transfer from the mcu to the endpoint fifo (mcu write data to the endpoint fifo). this bit defines the direction of data transfer between the mcu and the endpoint fifo. when the tx bit is set to high, this means that the mcu desires to write data to the endpoint fifo. after the mcu write operation has been complete, this bit has to be cleared to zero before terminating fifo request to indicate the end of data transfer. for a mcu read operation, this bit has to be cleared to zero to show that the mcu desires to read data from the endpoint fifo and has to be set to high before terminating fifo request to indicate the end of data transfer after the completion of mcu read operation. bit 0 request : fifo request control 0: no operation. 1: request the desired fifo. this bit is used to request the operation of the desired fifo. after selecting the desired endpoint, the fifo can be requested by setting this bit to high. after completion, this bit has to be cleared to zero. the mcu can communicate with the endpoint fifo by setting the corresponding registers, whose addresses are listed in the following table. after reading the current data, the next data will show af - ter 2 s, used to check the endpoint fifo status and responds to the misc register, if a read/write ac - tion is still being implemented. some timing constrains are listed here. by setting the misc register, the mcu can perform reading, writing and clearing actions. there are some examples shown in the following for the endpoint fifo reading, writing and clearing. actions misc setting flow and status check whether fifon can be read or not 00h01h delay 2 s, check 41h (ready) or 01h (not ready)00h check whether fifon can be written or not 02h03h delay 2 s, check 43h (ready) or 03h (not ready)02h read fifon sequence 00h01h delay 2 s, check 41h read* from fifon register and check not ready (01h) 03h02h write fifon sequence 02h03h delay 2 s, check 43h write* to fifo0 register and check not ready (03h) 01h00h read 0-sized packet sequence from fifo0 00h01h delay 2 s, check 81h clear len0 (01h)03h02h. write 0-sized packet sequence to fifon 02h03h delay 2s01h00h. note *: there are 2 s existing between 2 reading actions or between 2 writing actions. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 123 december 2, 2011 ! j ! # ! $ ' c - ( 9 ! j ! # ! $ ' c - ( 9
setio register the setio register is used to configure the endpoint fifo as in pipe or out pipe. b i t76543210 name setio5 setio4 setio3 setio2 setio1 datatg r/w r r r/w r/w r/w r/w r/w r/w por00111110 bit 7~6 unimplemented, read as 0. bit 5~1 setio5~setio1 : endpoint 5 fifo ~ endpoint fifo1 pipe direction control. 0: the corresponding endpoint fifo is configured as out pipe. 1: the corresponding endpoint fifo is configured as in pipe. if the related setio bit is set to 1 , the corresponding endpoint fifo is configured as in pipe for in token operation. otherwise, the corresponding endpoint fifo is configured as out pipe for out token operation. the purpose of this function is to avoid the usb host from abnormally sending only an in token or out token and disable the related endpoint. bit 0 datatg : data0 toggle bit 0: no operation. 1: data0 will be sent first. as the usb specification defined, when the usb host sends a set configuration setup token, the data pipe should send the data0 (data toggle) first. therefore, when the usb device receives a set configuration setup token, user needs to set d atatg bit to 1 and then clear it to zero after a 2 s delay to generate a positive pulse with 2 s pulse width to make sure that the next data will send a data0 first. fifo0~fifo5 registers the fifo0~fifo5 registers are used for data transactions between the usb device and the usb host. the mcu reads data from or writes data to the fifos via the application program to complete data interchange. for interrupt transfer it is supported by fifo0~fifo2 and fifo4, while it is supported by fifo3 and fifo5 for bulk transfer . label type por umisc setting flow and status fifo0 r/w xxxx xxxx data pipe for endpoint 0, depth = 8 bytes fifo1 r/w xxxx xxxx data pipe for endpoint 1, depth = 8 bytes fifo2 r/w xxxx xxxx data pipe for endpoint 2, depth = 8 bytes fifo3 r/w xxxx xxxx data pipe for endpoint 3, depth = 64 bytes fifo4 r/w xxxx xxxx data pipe for endpoint 4, depth = 8 bytes fifo5 r/w xxxx xxxx data pipe for endpoint 5, depth = 64 bytes x means unknown. rev. 1.00 124 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
uic register the uic register is used to control the interrupt request for each endpoint. interrupts can be enabled or disabled independently if the corresponding endpoint fifo pipes are enabled. b i t76543210 name eu5i eu4i eu3i eu2i eu1i eu0i r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 unimplemented, read as 0. bit 5~0 eu5i~eu0i : usb endpoint 5 ~ endpoint 0 interrupt control as being accessed. 0: disable the corresponding endpoint interrupt as it is accessed. 1: enable the corresponding endpoint interrupt as it is accessed. if the related endpoint fifo pipe is enabled and the corresponding endpoint interrupt is enabled, the usb interrupt for endpoint access will occur. then an interrupt signal pulse will be generated sent to mcu to get the attentions from the host mcu. ntim register the ntim register is used to control the nak token interrupt for each endpoint. the nak token interrupt can be masked independently by controlling the ntim register if the nak token interrupt global mask control nmi in sies register is set to 1. b i t76543210 name nti5m nti4m nti3m nti2m nti1m nti0m r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 unimplemented, read as 0. bit 5~0 nti5m~nti0m : usb endpoint 5 ~ endpoint 0 nak token interrupt mask control. 0: the corresponding endpoint nak token interrupt is not masked. 1: the corresponding endpoint nak token interrupt is masked. if the nak token interrupt global mask control is set to 1 and the corresponding endpoint nak token interrupt is not masked, the nak token interrupt will occur when the usb device sends a nak token to the usb host. then an interrupt signal pulse will be generated sent to the host mcu to get the attentions from the host mcu. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 125 december 2, 2011
pipe register the pipe register is used to control that the fifo pipe for each endpoint is enabled or disable. the endpoint access interrupt can be controlled independently by configuring the uic register if the corresponding endpoint fifo pipe is enabled. b i t76543210 name ep5e ep4e ep3e ep2e ep1e r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~6 unimplemented, read as 0. bit 5~1 ep5e~ep1e : usb endpoint 5 ~ endpoint 0 fifo pipe enable control. 0: the corresponding endpoint fifo pipe is disabled. 1: the corresponding endpoint fifo pipe is enabled. if the corresponding endpoint fifo pipe is disabled, the read/write operations to the related endpoint fifo pipe are not available. if the corresponding endpoint fifo pipe and the interrupt are both enabled, the related usb endpoint interrupt will be generated as the interrupt trigger events occur. otherwise, if the endpoint fifo pipe or the endpoint interrupt is disabled, the corresponding endpoint interrupt will not be generated. bit 0 unimplemented, read as 0. usb interface suspend mode and wake-up usb suspend mode the mcu and usb module are powered down independently of each other. the method of powering down the mcu is covered in the previous mcu section of the datasheet. the usb module must be powered down before the mcu is powered down. if there is no signal on the usb bus for over 3ms, the devices will go into a suspend mode. the suspend indication bit susp, bit 0 of the usc register, will be set to 1 and a usb interrupt will be generated to indicate that the device should jump to the suspend state to meet the 500 a usb suspend current specification. in order to meet the 500 a suspend current, the firmware should disable the usb clock by clearing the usb clock enable control bit usbcken in the ucc register to 0. also the usb pll circuitry control bits known as pll should be set to 1 to disable the usb pll function. the suspend current is about 400 a. usb host wake-up when the resume signal is asserted by the usb host, the usb device will wake up the mcu with a usb interrupt and the resume indication bit resume in the usc register will be set. in order to make the device function properly, the program must set the usbcken bit in the ucc register to 1 and clear the pll bit in the usc register to 0 . when the resume signal is de-asserted by the usb host, the usb device actually leaves the suspend mode and the usb host will communicate with the usb device. the susp bit will be cleared as well as the resume bit when the usb device really leaves the suspend mode. so when the mcu is detecting the suspend bit, the resume bit should be stored and taken into consideration. the following diagram shows the relationship between the susp and resume bits and interrupt signal. rev. 1.00 126 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces ! !
suspend and host wake-up
usb remote wake-up as the device has a remote wake-up function, it can wake up the usb host by sending a wake-up pulse by setting the rmwk bit in the usc register to 1 for 2 s and then setting the rmwk bit to 0 . once the usb host receives a wake-up signal from the device, it will send a resume signal to the device. the timing is as follows: usb interrupt structure several individual usb conditions can generate a usb interrupt. when these conditions exist, an interrupt pulse will be generated to get the attention of the microcontroller. these conditions are the usb suspended, usb resume, usb reset and usb endpoint fifo access events. when the usb interrupt caused by any of these conditions occurs, if the corresponding interrupt control in the host mcu is enabled and the stack is not full, the program will jump to the corresponding interrupt vector where it can be serviced before returning to the main program. for the usb endpoint fifo access event, there are the corresponding indication flags to indicate which endpoint fifo is accessed. as the endpoint fifo access flag is set, it will generate a usb interrupt signal if the associated endpoint fifo pipe and interrupt control are both enabled. the endpoint fifo access flags should be cleared by the application program. as the usb suspended, usb resume or usb reset condition occurs, the corresponding indication flag, known as susp, resume and urst bits, will be set and a usb interrupt will directly generated without any associated interrupt control being enabled. the susp, resume and urst bits are read only and set or cleared by the usb sie. for a usb interrupt occurred to be serviced, in addition to the bits for the corresponding interrupt enable control in usb module being set, the global interrupt enable control and the related interrupt enable control bits in the host mcu must also be set. if these bits are not set, then no interrupt will be serviced. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 127 december 2, 2011

9 : 7 + ( 9 : 7 7

!
!
5 5

) 7 (

) + '

) 7 ' + 7

) ' + ' usb interrupt structure ;
+ @
, a + , 8 @
, a suspend and remote wake-up
digital to analog converter dac the device includes a 12-bit digital to analog converter function. this function allows digital data contained in the device to generate audio signals. operation the data to be converted is stored in two registers dal and dah. the dah register stores the highest 8-bits, da11~da4, while dal stores the lowest 4-bits, da3~da0. an additional control register, dactrl, provides overall dac on/off control in addition to a 3-bit 8-level volume control. the dac output is channeled to pin aud which is pin-shared with i/o pin pa2. when the dac is enabled by setting the dacen bit high, then the original i/o function will be disabled, along with any pull-high resistor options. the dac output reference voltage is the power supply voltage vdd. dah register b i t76543210 name da11 da10 da9 da8 da7 da6 da5 da4 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 da11~da4 : audio output dac high byte data. 0: usb reset signal can no reset the mcu 1: usb reset signal will reset the mcu dal register b i t76543210 name da3 da2 da1 da0 r/w r/w r/w r/w r/w p o r00000000 bit 7~4 da3~da0 : audio output dac low byte data. bit 3~0 unimplemented, read as 0. dactrl register b i t76543210 name vol2 vol1 vol0 dacen r/w r/w r/w r/w r/w por00000000 bit 7~5 vol2~vol0 : audio output volume control. the audio output is at maximum volume if these bits are set to 111b while the audio output is at minimum volume if these bits are set to 000b. bit 4~1 unimplemented, read as 0. bit 0 dacen : dac enable control 0: dac is disabled 1: dac is enabled rev. 1.00 128 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
dc/dc converter and ldo the device contains a dc/dc converter and an ldo to provide the power supply for the smart card interface pins and the external smart card. the dc/dc converter is a pfm step-up dc/dc converter with high efficiency and low ripple. it requires only three external components to provide an output voltage of either 3.8v or 5.5v selected by the dc/dc output voltage selection bit vsel in the dc2dc register. the dc/dc voltage output is connected to an external pin as well as being connected to the ldo input. it also contains an enable control bit, dcen, in the dc2dc register to reduce power consumption when in the power down mode. if the smart card voltage output is switched to 0v by clearing the selection bits vc [1:0] in the ccr register, the dc/dc converter will automatically be turned off even if the enable control bit dcen is set to 1 . the ldo is a three-terminal high current low voltage dropout regulator with over current protection. it supports three output voltages of 1.8v, 3.0v or 5.0v selected by the smart card voltage selection bits vc1 and vc0 in the ccr register. it can deliver a maximum output current of 20ma, 50ma and 55ma when the ldo output voltage is 1.8v, 3.0v and 5.0v respectively. dc2dc register b i t76543210 name dcen vsel r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0. bit 1 dcen : dc/dc enable control 0: dc/dc converter disabled 1: dc/dc converter enabled this bit is used to control the dc/dc converter function. if this bit is set to 1 , the dc/dc output voltage is selected by the vsel selection bit. if this bit is cleared to 0, the dc/dc converter function is disabled and the output voltage is equal to the value of (v dd v diode ). bit 0 vsel : dc/dc output voltage selection 0: dc/dc output voltage is 3.8v 1: dc/dc output voltage is 5.5v HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 129 december 2, 2011 vdd dc/dc converter self vo ldo dcen vsel vc1 cvss crdvcc vc0 crst cc8 vss smart card interface pins cdet v dd
smart card interface the device contains a smart card interface compatible with the iso 7816-3 standard. this interface includes the card insertion/removal detection, uart interface control logic and data buffers, power control circuits, internal timer counters and control logic circuits to perform the required smart card operations. the smart card interface acts as a smart card reader to facilitate communication with the external smart card. the overall functions of the smart card interface is control by a series of registers including control and status registers. as the complexity of iso7816-3 standard data protocol does not permit comprehensive specifications to be provided in this datasheet, the reader should therefore consult other external information for a detailed understanding of this standard. interface pins to communicate with an external smart card, the internal smart card interface has a series of external pins known as crdvcc, crst, cclk, cio, cc4, cc8 and cdet. the crdvcc pin is the power supply pin of the external smart card and the smart card interface pins described above except the cdet pin. it can output several voltage levels as selected by the vc1 and vc0 selection bits. the crst pin is the reset output signal which is used to reset the external smart card. together with the internal crst control bit the mcu can control the crst pin level by writing specific data to the crst bit and obtain the crst pin status by reading the crst bit. the cclk pin is the clock output signal used to communicate with the external smart card together with the serial data pin, cio. the operation of cclk and cio can be selected as the uart mode automatically driven by the uart control circuits, or the manual mode controlled by configuring the internal cclk and cio bits respectively by the application program. the cdet pin is the external smart card detection input pin. when the external smart card is inserted or removed, it can be detected and generate an interrupt signal which is sent to mcu if the corresponding interrupt control bit is enabled. the cc4 and cc8 pins are used as i/o pins and are controlled by the corresponding cc4 and cc8 bits. card detection if an external smart card is inserted, the internal card detector can detect this insertion operation and generate a card insertion interrupt. when the card is present and detected, the power-on sequence for the external smart card should be activated by the application programs to supply power for the external smart card. similarly if the card is removed, the internal card detector can also detect the removal and consequently generate a card removal interrupt. like the card insertion operation, the card removal deactivation procedure defined in the iso 7816-3 standard should be activated by the application programs. rev. 1.00 130 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces crdvcc elementary time unit (etu) guard time counter (gtc) waiting time counter (wtc) f crd uart control circuits uart tx/rx buffers interrupt registers interrupt to mcu power control cdet card detection crst cclk cio cc4 cc8 i/o control clock control f etu f etu f gtc f wtc control registers crdvcc v dd smcen
the card detector can support two kinds of card detect switch mechanisms. one is a normally open switch mechanism when the card is not present and the other is a normally closed switch mechanism. after noting which card detect switch mechanism type is used, the card switch selection should be configured by setting the selection bit cdet in the ccr register to correctly detect the card presence. no matter what type of the card switch is selected by configuring the cdet bit, the card insertion/removal flag, cirf, in the csr register will be set to 1 when the card is actually present on the cdet pin. note that there is no hardware de-bounce circuits in the card detector. any change of the cdet pin level will cause the cirf bit to change. the required de-bounce time should be handled by the application program. there is a pull high resistor integrated in the card detector. a configuration option can determine whether the pull high resistor is internally connected to the cdet pin. internal time counter etu, gtc, wtc for proper data transfer, some timing purposed setting procedures must be executed before the smart card interface can begin to communicate with the external card. there are three internal counters named elementary time unit (etu), guard time counter (gtc) and waiting time counter (wtc) which are used for the timing related functions in the smart card interface operation. elementary time unit etu the elementary time unit (etu) is an 11-bit up-counting counter and generates the clock, denoted as f etu to be used as the operating frequency for the uart transmission and reception in the smart card interface. the clock source of the etu comes from the smart card clock named f crd derived from the high speed clock f m . the f crd clock frequency can be equal to the frequency of f m ,f m /2, f m /3 or f m /4 selected by the smart card clock source selection bits, crdcks1 and crdcks0. the data transfer of the uart interface is a character frame based protocol, which is basically consists of a start bit, 8-bit data and a parity bit. the time period t etu (1/f etu ), generated by the etu, is the time unit for uart character bit. there are two registers related to the etu known as the low byte etu register cetu0 and the high byte etu register cetu1, which store the expected contents of the etu. each time the high byte etu register cetu1 is written, the etu will reload the new written value and restart counting. the elementary time unit t etu is obtained from the following formula. t etu = f d x 1 f f: clock rate conversion integer d: baud rate adjustment integer f: clock rate of smart card the values of f and d, as they appear in the above formula, will be obtained from the answer-to-reset packet sent from the external smart card to the smart card interface, the first time the external smart card is inserted. when the smart card interface receives this information, the values which should be written into the cetu0 and cetu1 can be calculated by f/d. as the value of the etu registers is obtained by the above formula, the calculation results of the value may not be an integer. if the calculation result is not an integer and is less than the integer n but greater than the integer (n-1), either the integer n or (n-1) should be written into the cetu0 and cetu1 registers depending upon whether the result is closer to n or (n-1). the integer n mentioned here is a decimal. if the calculation result is close to the value of (n-0.5), the compensation mode should be enabled by setting the compensation enable control bit comp in the cetu1 register to 1 for successful data transfer. when the result is close to the value of (n-0.5) and the compensation mode is enabled, the value written into the cetu0 and cetu1 registers should be n and then the etu will generate the time unit sequence with n clock cycles and next (n-1) clock cycles alternately and so on. this results in an average time unit of (n-0.5) clock cycles and allows the time granularity down to a half clock cycle. note that the etu will reload the etu registers value and restart counting at the time when the start bit appears in the uart mode. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 131 december 2, 2011
guard time counter gtc the guard time counter (gtc) is a 9-bit up-counting counter and generates the minimum time duration known as a character frame denoted as t gtc between two successive characters in a uart transmission. the clock source of the gtc comes from the etu named f etu . the character transmission rate of the uart interface is controlled by t gtc generated by the gtc. there are two registers related to the gtc known as the low byte gtc register, cgt0, and the high byte gtc register, cgt1, which store the expected value of the gtc. the gtc value will be reloaded at the end of the current guard time period. note that the guard time between the last character received from the smart card and the next character transmitted by the smart card interface (smart card reader) should be managed by the application program. waiting time counter wtc the waiting time counter (wtc) is a 24-bit down-counting counter and generates a maximum time duration denoted as t wtc for the data transmission. the clock source of the wtc comes from the etu named f etu . the data transfer is categorized into 2 types. one is the character transfer which means each data transmission or reception is one character while the other is the blocks transfer which means each data transmission or reception is more than one character. the information related to the data transfer type or the number of the characters to be transferred is contained in the answer-to-reset packet. there are three data registers for the wtc known as the low byte wtc register cwt0, the middle byte wtc register cwt1 and the high byte wtc register cwt2, which store the expected wtc values. the wtc can be used in both uart mode and manual mode and can reload the value at specific conditions. the function of the wtc is controlled by the wten bit in the ccr register or by a configuration option. when the uart interface is set to be operated in the uart mode and the wtc is enabled, the updated cwt value will be loaded into the wtc as the start bit is detected. if the uart interface is set to be operated in the manual mode and the wtc is enabled, the updated cwt value will be loaded into the wtc. regardless of whether it is in the uart mode or manual mode, if the wten bit is cleared to 0 , the updated cwt value will not be loaded into the wtc until the wten bit is again set to 1 and the wtc underflows from the current loaded value. when the transfer type is configured as a character transfer, the wtc will generate the maximum timeout period of the character waiting time (cwt). if the transfer type is configured as a block transfer, the wtc will generate the character waiting time (cwt) except for the last character. the block waiting time (bwt) should be loaded into the wtc data registers before the start bit of the last transmitted character occurs. as the start bit of the last transmitted character occurs, the bwt value will be load into the wtc. then the smart card may be expected to transmit data to the smart card interface in the bwt duration. if the smart card does not transmit any data characters, the wtc will underflow. when the wtc underflows, the corresponding request flag, wtf, in the csr register rev. 1.00 132 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces cio start bit p parity bit character comp=0 comp=1 nnnnnnnnnn n n-1 nnnn n-1n-1n-1n-1 (1 t etu =n clocks) (cetu=n) t etu data bits character frame and compensation mode
will be set. the waiting time underflow pending flag, wtp, in the cipr register, will also be set if the interrupt enable control bit, wte, in the cier register is set. then an interrupt will be generated to notify the mcu that the smart card has not responded to the smart card reader. note that if the wtc value is set to zero, the wft bit will be equal to 1 . uart interface data transfer with the external smart card is implemented into two operating modes. one is the uart mode while the other is the manual mode. the data transfer mode is selected by the uart mode selection bit, umod, in the ccr register. when the umod bit is set to 1 , the uart mode is enabled and data transfer operates in the uart mode. otherwise, data transfer operates in the manual mode if the umod bit is set to 0 . the uart interface is a half-duplex interface and communicates with the external smart card via the cclk and cio pins. the cio pin can be selected to be connected to a pull high resistor by a configuration option. after a reset condition the uart interface is in the reception mode but the uart mode is disabled. when the uart mode is selected, data transfer is driven by the uart circuits automatically through the cclk and cio pins. there are two data registers related to data transmission and reception, ctxb and crxb, which store the data to be transmitted and received respectively. if a character is written into the ctxb register in the uart mode, the uart interface will automatically switch to the transmission mode from the reception mode after a reset. when the uart transmission or reception has finished, the corresponding request flag named txcf or rxcf is set to 1 . if the transmit buffer is empty, the transmit buffer empty flag, txbef, will be set to 1 . the uart interface supports a parity generator and a parity check function. as the parity error occurs during a data transfer, the corresponding request flag named, parf, in the csr register will be set to 1 . once the parf bit is set to 1 , the parity error pending flag parp in the cipr register will be set to 1 if the relevant interrupt control bit is enabled. then an interrupt signal will be generated and sent to the mcu. there is a character repetition function supported by the uart interface when a parity error occurs. the character repetition function is enabled by setting the crep bit to 1 and then the repetition function is activated when the parity error occurs during data transfers. the repetition times can be selected to be 4 or 5 times by a configuration option. when the crep bit is set to 1 and the repetition times is set to 4 times, the uart interface, if in the transmission mode, will transmit the data repeatedly for 4 times at most when an error signal occurs. if the data transmitted by the uart interface is received by the smart card receiver without a parity error during these 4 transmissions, the transmission request flag, txcf, of the uart interface will be set to 1 and the parf bit will be cleared to 0 . if the uart interface is informed that there is still an error signal during the 4 transmissions, the parity error flag parf of the uart interface will be set to 1 at the 5th transmission but the transmission request flag txcf will not be set. if the uart interface is in the reception mode, it will inform the smart card transmitter that there is a parity error for at most 4 times. if the data transmitted by the smart card transmitter is received by the uart interface without a parity error during the 4 receptions, the reception request flag, rxcf, of the uart interface will be set to 1 and the parf bit will be cleared to 0 . if the uart interface informs the smart card that there is still an error signal during the 4 receptions, the parity error flag, parf, of the uart interface will be set to 1 at the 5th reception as well as the transmission request flag, rxcf. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 133 december 2, 2011 smart card interface smart card char 0 char 1 char n program the bwt bwt program the cwt char 1 cwt start bit start bit char 0 wtc is reloaded on start bit
if the crep bit is set to 0 and the uart interface is in the reception mode, both the parf and rxcf bits will be set to 1 when the data with parity error has been received but the character repetition will not be activated. if the uart interface is in the transmission mode and the crep bit is set to 0 , it acts as a normal transmitter and the txcf bit is set to 1 after the data has been transmitted. it has no effect on parf bit. when data is selected to be transferred in the manual mode by setting the umod bit to 0 , the data is controlled by the control bit, cio, in the cccr register. the value of the cio bit will be reflected immediately on the cio pin in the manual mode. note that in the manual mode the character repetition function is not used as well as the related flags and all the data transfer is handled by the application program. the clock used to drive the external smart card that appears on the cclk pin can be derived from the internal clock source known as the fcrd clock or the control bit, cclk, in cccr register and selected by the smart card selection bit, clksel, in the cccr register. when clksel is set to 1 to select the clock source for the smart card to be fcrd, a configuration option can determine whether the clock output on the cclk pin, which comes from the fcrd clock, is to be divided by 2 or not. if users wish to handle the cclk clock manually, the clksel bit should first be set to 0 and then the value of the cclk bit will be present on the cclk pin. when the smart card is first inserted, the data direction convention is sent first in the answer-to-reset packet to inform the smart card interface whether the msb of the data is sent first or the lsb is sent first. if the direction convention used by the smart card is the same as the convention used by the smart card interface, the uart interface will generate a reception interrupt if the reception interrupt is enabled without a parity error flag. otherwise, the uart interface will generate a reception interrupt and the parity error flag will be asserted. by checking the parity error flag the smart card interface can know if the data direction convention is correct or not. power control when the smart card is first inserted and detected, the power-on sequence for the external smart card should be activated by the application programs to supply power to the external smart card. all the information necessary for the smart card interface to communicate with the external card is contained in the answer-to-reset packet including the data transfer type (character or blocks), the data direction convention (msb or lsb first), the clock rate information (etu, gtc or wtc), etc. the voltage level supplied to the smart card is also defined in the answer-to-reset packet. the smart card power supply voltage level is generated by the ldo and selected by the smart card power supply voltage selection bits vc1 and vc0 in the ccr register. when the external smart card is inserted, the application program should set the crdvcc pin to the expected voltage level defined in the answer-to-reset packet. similarly, the power deactivation procedure defined in the iso 7816-3 standard should also be properly arranged by the application programs when the external smart card is removed. after the external smart card is removed, the smart card interface circuitry enable control bit, cvcc, in the cccr register will be automatically cleared to zero to prevent the smart card interface module from being re-modified. the crdvcc pin voltage level and the related smart card interface register contents will remain unchanged but the relevant smart card interface pins including crst, cclk, cio, cc4 and cc8 pins will be kept at a low level when the external card is removed. the power control circuitry provides the card voltage and current indicators to avoid malfunctions. when the card voltage is within its specified range, the card voltage flag vcok will be set to 1 .if the card is not in the specified range, the vcok flag will be cleared to 0 to indicate that the card voltage is not within the specified range. as the vcok bit changes from 1 to 0, the corresponding pending flag named vcp in cipr register will be set to 1 if the card voltage error interrupt control vce in the cier register is enabled. rev. 1.00 134 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
when the current consumed by the external smart card is within the range specified in the iso 7816-3 standard, the card current overload flag iovf will remain at a 0 value. if the card current is not within the specified range, the iovf flag will be set to 1 to indicate that the card current is too high. as the iovf bit is set to 1, the relevant pending flag, iovfp, in the cipr register will also be set to 1 if the card current overload interrupt control enable bit, iovfe, in the cier register is enabled. card class classa classb classc operation voltage 3.6~5.5 2.5~5.5 2.5~5.5 operation frequency maximum 20mhz (v cc 4.0v) 20mhz (v cc 4.0v) 20mhz (v cc 4.0v) 12mhz (v cc 3.6v) 12mhz (v cc 3.0v) 12mhz (v cc 3.0v) smart card class operating conditions smart card interrupt structure there are several conditions for the smart card that to generate a smart card interrupt. when these conditions exist, an interrupt pulse will be generated to get the attention of the microcontroller. these conditions are a smart card insertion/removal, a smart card voltage error, a smart card current overload, a waiting time counter underflow, a parity error, an end of a character transmission or reception and an empty transmit buffer. when a smart card interrupt is generated by any of these conditions, then if the corresponding interrupt enable control bit in the host mcu is enabled and the stack is not full, the program will jump to the corresponding interrupt vector where it can be serviced before returning to the main program. for smart card interrupt events, except for card insertion/removal events, there are corresponding pending flags which can be masked by the corresponding interrupt enable control bits. when the related interrupt enable control is disabled, the corresponding interrupt pending flag will not be affected by the request flag and no interrupt will be generated. if the related interrupt enable control is enabled, the relevant interrupt pending flag will be affected by the request flag and then the interrupt will be generated. the pending flag register cipr is read only and once the pending flag is read by the application program, it will be automatically cleared while the related request flag should be cleared by the application program manually. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 135 december 2, 2011 csr register card insertion/removal request flag cirf transmit buffer empty request flag txbef end of transmission request flag txcf end of reception request flag rxcf wtc underflow request flag wtf parity error request flag parf card current overload request flag iovf card voltage status request flag vcok interrupt signal to mcu transmit buffer empty pending flag txbep end of transmission pending flag txcp end of reception pending flag rxcp wtc underflow pending flag wtp parity error pending flag parp card current overload pending flag iovfp card voltage error pending flag vcp cipr register txbee 0 1 txce 0 1 rxce 0 1 pare 0 1 wte 0 1 iovfe 0 1 vce 0 1 cier register interrupt signal to mcu smart card interrupt structure
when a smart card insertion/removal event occurs, the card insertion/removal request flag, cirf, will be set and a smart card insertion/removal interrupt will be directly generated without any associated interrupt control being enabled. for a smart card interrupt occurred to be serviced, in addition to the bits for the corresponding interrupt enable control in the smart card interface being set, the global interrupt enable control and the related interrupt enable control bits in the host mcu must also be set. if these bits are not set, then no interrupt will be serviced. programming considerations since the whole smart card interface is driven by the clock f crd which is derived from the high speed oscillator clock f m , the smart card interface will not operate, even interface registers read/write operations, if the high speed oscillator clock f m is stopped. for example, if the mcu clock source is switched to the low speed clock f sl which comes from the low speed oscillator lxt or lirc, then all operations related to the smart card interface are not performed. if the frequency of the clock f crd is slower than the frequency of the high speed oscillator clock f m divided by 2, it will result in synchronization problems between two different clock domains known as the cpu clock and the smart card interface clock. smart card interface status and control registers there are several registers associated with the smart card function. some of the registers control the overall function of the smart card interface as well as the interrupts, while some of the registers contain the status bits which indicate the smart card data transfer situations, error conditions and power supply conditions. also there are two registers for the uart transmission and reception respectively to store the data received from or to be transmitted to the external smart card. addres s name por state bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 50h ccr 0000 0000 rstcrd cdet vc1 vc0 umod wten crep conv 51h csr 1000 0000 txbef cirf iovf vcok wtf txcf rxcf parf 52h cccr 0-xx x0x0 clksel cc8 cc4 cio cclk crst cvcc 53h cetu1 0000 0001 comp etu10 etu9 etu8 54h cetu0 0111 0100 etu7 etu6 etu5 etu4 etu3 etu2 etu1 etu0 55h cgt1 ---- ---0 gt8 56h cgt0 0000 1100 gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0 57h cwt2 0000 0000 wt23 wt22 wt21 wt20 wt19 wt18 wt17 wt16 58h cwt1 0010 0101 wt15 wt14 wt13 wt12 wt11 wt10 wt9 wt8 59h cwt0 1000 0000 wt7 wt6 wt5 wt4 wt3 wt2 wt1 wt0 5ah cier 0-00 0000 txbee iovfe vce wte txce rxce pare 5bh cipr 0-00 0000 txbep iovfp vcp wtp txcp rxcp parp 5ch ctxb 0000 0000 smart card transmission buffer (tb7~tb0) 5dh crxb 0000 0000 smart card reception buffer (rb7~rb0) smart card interface register summary rev. 1.00 136 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
ccr register the ccr register contains the control bits for the smart card interface. further explanation on each bit is given below: b i t76543210 name rstcrd cdet vc1 vc0 umod wten crep conv r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 rstcrd : reset control for the smart card interface 0: no smart card interface reset 1: reset the smart card interface (except rstc bit) this bit is used to reset the whole smart card interface except the rstcrd bit. it is set and cleared by application program. bit 6 cdet : card switch type selection 0: switch is normally opened if no card is present 1: switch is normally closed if no card is present this bit is set and cleared by application program to configure the switch type of the card detector. bit 5~4 vc1~vc0 : card voltage selection 00: card voltage is equal to 0v 01: card voltage is equal to 1.8v 10: card voltage is equal to 3v 11: card voltage is equal to 5v these bits are set and cleared by application program to select the voltage level for the external smart card. bit 3 umod : uart mode selection 0: data transfer in manual mode. 1: data transfer in uart mode. this bit is set and cleared by application program to configure the data transfer type. if it is cleared to 0, the cio pin status is the same as the value of the cio bit in the cccr register. if it is set to 1, the cio pin is driven by the internal uart control circuitry. before the data transfer type is switched from manual mode to uart mode, the cio bit must be set to 1 to avoid a uart malfunction. bit 2 wten : waiting time counter (wtc) counting control 0: wtc tops counting. 1: wtc starts to count. the wten bit is set and cleared by application program. when the wten bit is cleared to 0, a write access to the cwt2 register will load the value held in the cwt2~cwt0 registers into the wtc. if it is set to 1, the wtc is enabled and automatically reloaded with the value in cwt2~cwt0 at each start bit occurrence. bit 1 crep : character repetition enable control at parity error condition 0: no retry on parity error 1: automatically retry on parity error the crep bit is set and cleared by application program. when the crep bit is cleared to 0, both the rxcf and parf flags will be set on parity error in reception mode after the data is received while the parf is set but the txcf is cleared in the transmission mode. if the crep bit is set to 1, the character retry will automatically be activated on parity error for 4 or 5 times depending upon the configuration option. in the transmission mode the character will be re-transmitted if the transmitted data is refused and then the parity error flag parf will be set at 5th or 6th transmission but txcf will not be set. in the reception mode if the received data has a parity error, the receiver will inform the transmitter for 4 or 5 times and then the parf and rxcf flags will both be set at 5th or 6th reception. bit 0 conv : data direction convention 0: lsb is transferred first. 1: msb is transferred first. this bit is set and cleared by the application program to select if the data is lsb transferred first or msb transferred first. when the direction convention is the same as the direction specified by the external smart card, only rxcf will be set to 1 without parity error. otherwise, both rxcf and parf will be set to 1 after the data is received. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 137 december 2, 2011
csr register the csr register contains the status bits for the smart card interface. further explanation on each bit is given below: b i t76543210 name txbef cirf iovf vcok wtf txcf rxcf parf r/wrrrrrr/wrr/w por10000000 bit 7 txbef : transmission buffer empty request flag 0: transmission buffer is not empty 1: transmission buffer is empty this bit is used to indicate if the transmit buffer is empty and is set or cleared by hardware automatically. bit 6 cirf : card insertion/removal request flag 0: no card is present. 1: a card is present this bit is used to indicate if a card is present and is set or cleared by hardware automatically. bit 5 iovf : card current overload request flag 0: no card current overload 1: card current overload the bit is set or cleared by hardware automatically and indicates whether the card current is overloaded. bit 4 vcok : card voltage status flag 0: card voltage is not in the specified range 1: card voltage is in the specified range the bit is set or cleared by hardware automatically and indicates whether the card voltage is in the specified range. bit 3 wtf : waiting time counter (wtc) underflow request flag 0: the wtc does not underflow. 1: the wtc underflows. this bit is set and cleared by application program and indicates if the wtc underflows. bit 2 txcf : character transmission request flag 0: no character transmitted request 1: a character has been transmitted the txcf bit is set by hardware and cleared by application program. if the bit is set to 1, it indicates that the character has been transmitted. bit 1 rxcf : character repetition request flag 0: no character received request 1: a character has been received the rxcf bit is set by hardware automatically and cleared after a read access to the crxb register by the application program. the rxcf bit will always be set to 1 when a character is received regardless of the result of the parity check. when the character has been received, the received data stored in the crxb register should be moved to the data memory specified by users. if the contents of the crxb register are not read before the end of the next character shifted in, the data stored in the crxb register will be overwritten. bit 0 parf : parity error request flag 0: no parity error request 1: parity error has been occurred this bit is set by hardware automatically and cleared by the application program. when a character is received, the parity check circuits will check that the parity is correct or not. if the result of the parity check is not correct, the parity error request flag, parf, will be set to 1. otherwise, the parf bit will remain at zero. rev. 1.00 138 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
cccr register the cccr register contains the control bits of the smart card interface pins. further explanation on each bit is given below: b i t76543210 name clksel cc8 cc4 cio cclk crst cvcc r/w r/w r/w r/w r/w r/w r/w r/w por00xxx0x0 x: unknown bit 7 clksel : smart card clock selection 0: the content of the cclk bit is present on the external cclk pin 1: the clock output on the external cclk pin comes from the f crd clock this bit is used to select the clock source on the external cclk pin. it is set and cleared by application program. it is recommended that to activate the clock at a known level a certain value should be programmed into the cclk bit before the clksel bit is switched from 1 to 0. bit 6 unimplemented, read as 0 bit 5 cc8 : cc8 pin control 0: the status of the external cc8 pin is 0 1: the status of the external cc8 pin is 1 the bit is set and cleared by application program to control the external cc8 pin status. the value written into this bit will be present on the external cc8 pin. reading this bit will return the status present on the cc8 pin. bit 4 cc4 : cc4 pin control 0: the status of the external cc4 pin is 0 1: the status of the external cc4 pin is 1 the bit is set and cleared by application program to control the external cc4 pin status. the value written into this bit will be present on the external cc4 pin. reading this bit will return the status present on the cc4 pin. bit 3 cio : cio pin control 0: the status of the external cio pin is 0 1: the external cio pin remains at an open drain condition this bit is available only if the umod bit in the ccr register is cleared to 0 (manual mode). it is set and cleared by application program to control the external cio pin status in manual mode. reading this bit will return the status present on the cio pin. a pull high resistor can be connected to the cio pin determined by a configuration option. bit 2 cclk : cclk pin control 0: the status of the external cclk pin is 0 1: the status of the external cclk pin is 1 this bit is available only if the umod bit in the ccr register is cleared to 0 (manual mode). the bit is set and cleared by application program to control the external cclk pin status in manual mode. reading this bit will return the current value in the register instead of the status present on the cclk pin. bit 1 crst : crst pin control 0: the status of the external crst pin is 0 1: the status of the external crst pin is 1 this bit is set and cleared by application program to control the external crst pin status to be used to reset the external smart card. reading this bit will return the present status of the crst pin. bit 0 cvcc : smart card interface circuitry enable control 0: smart card interface circuitry is disabled 1: smart card interface circuitry is enabled. this bit is set and cleared by application program to control the smart card interface module is switched on or off when the external card is present. if the external card is not present on the cdet pin, this bit is not available to control the smart card interface circuitry and will automatically be cleared to 0 by hardware. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 139 december 2, 2011
cetu registers the cetu registers, cetu1 and cetu0, contain the specific values determined by the formula described in the etu section. it also includes a control bit of the compensation function for the etu time granularity. note that the value of the etu must be in the range of 00ch to 7ffh. to obtain the maximum etu decimal value of 2048, a 000h value should be written into the etu10~etu0 bits. further explanation on each bit is given below: b i t76543210 name comp etu10 etu9 etu8 r/w r/w r/w r/w r/w por00000001 bit 7 comp : compensation function enable control 0: compensation function is disabled. 1: compensation function is enabled. this bit is set and cleared by application program used to control the compensation function. the compensation function has been described and more details can be obtained in the etu section. bit 6~3 unimplemented, read as 0. bit 2~0 etu10~etu8 : bit 10~8 of the etu value the bits are set and cleared by application program to modify the etu values. writing to the cetu1 register will reload the updated value into the etu counter. cetu0 register b i t76543210 name etu7 etu6 etu5 etu4 etu3 etu2 etu1 etu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por01110100 bit 7~0 etu7~etu0 : bit 7~0 of the etu value the bits are set and cleared by application program to modify the etu values. rev. 1.00 140 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
cgt registers the cgt registers named cgt1 and cgt0 store the specific gtc values obtained from the answer-to-reset packet described in the gtc section. note that the gtc values must be in the range from 00ch to 1ffh. further explanation on each bit is given below: cgt1 register b i t76543210 name gt8 r/w r/w por00000000 bit 7~1 unimplemented, read as 0 bit 0 gt8 : bit 8 of the gtc value cgt0 register b i t76543210 name gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00001100 bit 7~0 gt7~gt0 : bit 7~0 of the gtc value the bits gt8~gt0 are set and cleared by application program to modify the gtc values. the up - dated gtc value will be loaded into the gtc counter at the end of the current guard time period. cwt registers the cwt registers, cwt2, cwt1 and cwt0, store the specific wtc value obtained from the answer-to-reset packet described in the wtc section. note that the gtc value must be in the range from 00ch to 1ffh. cwt2 register b i t76543210 name wt23 wt22 wt21 wt20 wt19 wt18 wt17 wt16 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 wt23~wt16 : bit 23~16 of the value cwt1 register b i t76543210 name wt15 wt14 wt13 wt12 wt11 wt10 wt9 wt8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00100101 bit 7~0 wt15~wt8 : bit 15~8 of the wtc value HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 141 december 2, 2011
cwt0 register b i t76543210 name wt7 wt6 wt5 wt4 wt3 wt2 wt1 wt0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por10000000 bit 7~0 wt7~wt0 : bit 7~0 of the wtc value the bits wt23~wt0 are set and cleared by application program to modify the gtc values. the re - load conditions of the updated wtc value are described in the wtc section. users can refer to the wtc section for more details. cier register the cier register contains the interrupt enable control bits for all of the interrupt events in the smart card interface. further explanation on each bit is given below: b i t76543210 name txbee iovfe vce wte txce rxce pare r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 txbee : transmit buffer empty interrupt enable control 0: disable 1: enable this bit is set and cleared by application program used to control the transmit buffer empty interrupt. if this bit is set to 1, the transmit buffer empty interrupt will be generated when the transmit buffer is empty. bit 6 unimplemented, read as 0 bit 5 iovfe : card current overload interrupt enable control 0: disable 1: enable this bit is set and cleared by application program and is used to control the card current overload interrupt. if this bit is set to 1, the card current overload interrupt will be generated when the card current is overloaded. bit 4 vce : card voltage error interrupt enable control 0: disable 1: enable this bit is set and cleared by application program and is used to control the card voltage error interrupt. if this bit is set to 1, the card voltage error interrupt will be generated when the card voltage is not in the specified range. bit 3 wte : waiting time counter underflow interrupt enable control 0: disable 1: enable this bit is set and cleared by application program and is used to control the waiting time counter underflow interrupt. if this bit is set to 1, the waiting time counter underflow interrupt will be generated when the wtc underflows. bit 2 txce : character transmission completion interrupt enable control 0: disable 1: enable this bit is set and cleared by application program and is used to control the character transmission completion interrupt. if this bit is set to 1, the character transmission completion interrupt will be generated at the end of the character transmission. rev. 1.00 142 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
bit 1 rxce : character reception completion interrupt enable control 0: disable. 1: enable. this bit is set and cleared by application program and is used to control the character reception completion interrupt. if this bit is set to 1, the character reception completion interrupt will be generated at the end of the character reception. bit 0 pare : parity error interrupt enable control 0: disable 1: enable this bit is set and cleared by application program and is used to control the parity error interrupt. if this bit is set to 1, the parity error interrupt will be generated when a parity error occurs. cipr register the cipr register contains the interrupt pending flags for all of the interrupt events in the smart card interface. these pending flags can be masked by the corresponding interrupt enable control bits. further explanation on each bit is given below: b i t76543210 name txbep iovfp vcp wtp txcp rxcp parp r/w r rrrrrr por00000000 bit 7 txbep : transmit buffer empty interrupt pending flag 0: no interrupt pending. 1: interrupt pending. this bit is set by hardware and cleared by a read access to this register using the application program. it is used to indicate if there is a transmit buffer empty interrupt pending or not. if the corresponding interrupt enable control bit is set to 1 and the transmit buffer is empty, this bit will be set to 1 to indicate that the transmit buffer empty interrupt is pending. bit 6 unimplemented, read as 0. bit 5 iovfp : card current overload interrupt pending flag 0: no interrupt pending. 1: interrupt pending. this bit is set by hardware and cleared by a read access to this register using the application program. it is used to indicate if there is a card current overload interrupt pending or not. if the corresponding interrupt enable control bit is set to 1 and the card current is overloaded, this bit will be set to 1 to indicate that the card current overload interrupt is pending. bit 4 vcp : card voltage error interrupt pending flag 0: no interrupt pending. 1: interrupt pending. this bit is set by hardware and cleared by a read access to this register using the application program. it is used to indicate if there is a card voltage error interrupt pending or not. if the corresponding interrupt enable control bit is set to 1 and the card voltage is not in the specified range, this bit will be set to 1 to indicate that the card voltage error interrupt is pending. bit 3 wtp : waiting time counter underflow interrupt pending flag 0: no interrupt pending. 1: interrupt pending. this bit is set by hardware and cleared by a read access to this register using the application program. it is used to indicate if there is a waiting time counter underflow interrupt pending or not. if the corresponding interrupt enable control bit is set to 1 and the wtc underflows, this bit will be set to 1 to indicate that the waiting time counter underflow interrupt is pending. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 143 december 2, 2011
bit 2 txcp : character transmission completion interrupt pending flag 0: no interrupt pending. 1: interrupt pending. this bit is set by hardware and cleared by a read access to this register using the application program. it is used to indicate if there is a character transmission completion interrupt pending or not. if the corresponding interrupt enable control bit is set to 1 and a character has been transmitted, this bit will be set to 1 to indicate that the character transmission completion interrupt is pending. bit 1 rxcp : character reception completion interrupt pending flag 0: no interrupt pending. 1: interrupt pending. this bit is set by hardware and cleared by a read access to this register using the application program. it is used to indicate if there is a character reception completion interrupt pending or not. if the corresponding interrupt enable control bit is set to 1 and a character has been received, this bit will be set to 1 to indicate that the character reception completion interrupt is pending. bit 0 parp : parity error interrupt pending flag 0: no interrupt pending. 1: interrupt pending. this bit is set by hardware and cleared by a read access to this register using the application program. it is used to indicate if there is a parity error interrupt pending or not. if the corresponding interrupt enable control bit is set to 1 and the parity error occurs, this bit will be set to 1 to indicate that the parity error interrupt is pending. ctxb register the ctxb register is used to store the data to be transmitted. b i t76543210 name tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tb7~tb0 : data bits 7~0 to be transmitted. crxb register the crxb register is used to store the received data. as the character has been received completely, the value in crxb register should be read to avoid the next character being overwritten. b i t76543210 name rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 rb7~rb0: bits 7~0 of the received data. rev. 1.00 144 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
configuration options configuration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. all options must be defined for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed system oscillator selection - f m external xtal oscillator (hxt), external rc oscillator (erc), internal rc oscillator (hirc) or external oscillator (ec) 2 external xtal oscilaltor (hxt) frequency selection: 455khz or 1mhz~12mhz 3 external oscillator (ec) clock filter control: enable or disable 4 internal rc oscillator (hirc) frequency selection: 4mhz, 8mhz or 12mhz 5 low speed system oscillator selection - f sl external 32.768khz xtal oscillator (lxt) or internal 32khz rc oscillator (lirc) 6 oscillator selection for f sub external 32.768khz xtal oscillator (lxt) or internal 32khz rc oscillator (lirc) 7 wdt clock selection for f s f sub or f sys /4 watchdog options 8 watchdog timer function: enable or disable 9 clrwdt instructions: 1 or 2 instructions 10 wdt time-out period: 2 12 /f s ,2 13 /f s ,2 14 /f s or 2 15 /f s time base option 11 time base time-out period selection: 2 12 /f s ,2 13 /f s ,2 14 /f s or 2 15 /f s buzzer options 12 i/o or buzzer output selection: pa0, pa1; bz, pa1 or bz, bz 13 buzzer output frequency selection: f s /2 2 ,f s /2 3 ,f s /2 4 ,f s /2 5 ,f s /2 6 ,f s /2 7 ,f s /2 8 or f s /2 9 pfd options 14 i/o or pfd output selection: pa3 or pfd 15 pfd source selection: pfd0 (from timer/event counter 0) or pfd1 (from timer/event counter 1) res pin option 16 i/o or resb pin selection: pc7 or res lvd/lvr options 17 lvd function: enable or disable 18 lvr function: enable or disable 19 lvr/lvd voltage: 2.1v/2.2v or 3.15v/3.3v or 4.2v/4.4v HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 145 december 2, 2011
no. options smart card interface options 20 cdet pin pull high function: enable or disable 21 cio pin pull high function: enable or disable 22 waiting time counter (wtc) function: enable or disable 23 character transfer repetition times selection: 4 times or 5 times sim option 24 serial interface module 0 (sim0) function: enable or disable 25 spi0 wcol bit function: enable or disable 26 spi0 csen bit function: enable or disable 27 i 2 c0 clock debounce time selection: disable, 1 system clock or 2 system clocks 28 serial interface module 1 (sim1) function: enable or disable 29 spi1 wcol bit function: enable or disable 30 spi1 csen bit function: enable or disable 31 i 2 c1 clock debounce time selection: disable, 1 system clock or 2 system clocks i/o pin power supply options 32 i/o or vddio power pin selection: pb3 or vddio 33 pb0~pb2 power supply selection (by bit): vdd or vddio 34 pb4~pb7 power supply selection (by bit): vdd or vddio 35 pc4 power supply selection: vdd or vddio rev. 1.00 146 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
application circuits HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 147 december 2, 2011 4 ' ' ! % 5 4 4 ' ' 6 2 4 % ' ! & - 4 9 , : 5 4 ' ' % 4 9 , : h : 5 : 9 / h : 9 9 / * 9 9 l 9 , 9 : 5 l l : 6 7 : 7 4 % ; ' ! 7 e ' 4 4 * * : , 8 / 7 h . 2 9 h 2 - $ 9 & $ 6 9 h $ - & $ 6 - % ' 9 h : 8 ! < 9 h ! < - = 9 & : : + + & * * & 7

instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be implemented within 1 s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. rev. 1.00 148 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 149 december 2, 2011
instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none rev. 1.00 150 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
mnemonic description cycles flag affected bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. 4. if the register in smart card interface is assessed by any instruction, the instruction cycle is additionally added by 1. HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 151 december 2, 2011
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z rev. 1.00 152 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cy - cle instruction. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con- junction with clr wdt2 and must be executed alternately with clr wdt2 to have ef- fect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con - junction with clr wdt1 and must be executed alternately with clr wdt1 to have ef - fect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 153 december 2, 2011
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain un - changed. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the con - tents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf rev. 1.00 154 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 155 december 2, 2011
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pend- ing when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data mem - ory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none rev. 1.00 156 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 re - places the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 157 december 2, 2011
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec- ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none rev. 1.00 158 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec - ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruc- tion. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the re- sult is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the re - sult is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is neg - ative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 159 december 2, 2011
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain un - changed. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following in - struction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none rev. 1.00 160 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces
tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 161 december 2, 2011
package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website ( http://www.holtek.com.tw/english/literature/package.pdf ) for the latest version of the package information. 144-pin lqfp (20mm 20mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.862 0.870 b 0.783 0.791 c 0.862 0.870 d 0.783 0.791 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 0 7 rev. 1.00 162 december 2, 2011 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces : : 7 7 * . : 9 = $ 2 : 9 - * ' * - - + ! 5 < 0 q ;
symbol dimensions in mm min. nom. max. a 21.90 22.10 b 19.90 20.10 c 21.90 22.10 d 19.90 20.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 0 7 HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 163 december 2, 2011
HT56RB688 tinypower tm a/d type smart card otp mcu with lcd, dac, iso 7816 and usb interfaces rev. 1.00 164 december 2, 2011 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

▲Up To Search▲

Price & Availability of HT56RB688

	To Download HT56RB688 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .